Skyworks Solutions Inc. 513FCA001142BAGR

Overview

513FCA001142BAGR from Skyworks Solutions is a dual-frequency crystal oscillator (XO) with factory-programmed frequencies of 100 MHz and 125 MHz, ±30 ppm total stability, 3.3 V supply, LVDS output format, and OE active-high on pin 1 in a 3.2 × 5.0 mm 6-pin package. It delivers low-jitter clocking for high-speed serial interfaces requiring precise dual-clock switching.

For engineers reviewing the 513FCA001142BAGR datasheet, 513FCA001142BAGR pinout, 513FCA001142BAGR application, or 513FCA001142BAGR equivalent, this page provides verified technical context, validated pin functions, confirmed dual-frequency operation, real-world jitter performance (0.25 ps RMS phase jitter, 12 kHz–20 MHz), and direct alternative part comparisons for FPGA/ASIC timing design.

Technical Context

The 513FCA001142BAGR implements Skyworks' DSPLL® synthesis architecture using a fixed crystal resonator and all-digital frequency synthesis to generate two user-selectable output frequencies (100 MHz and 125 MHz) without external components. Frequency selection is controlled via the FS pin (active-high logic), while OE enables/disables outputs with runt suppression.

It integrates an on-chip LDO regulator for supply noise rejection and supports LVDS differential signaling with 100 Ω line-line termination, 48–52% duty cycle, and 0.25–0.55 ps RMS phase jitter (12 kHz–20 MHz integration). Operation is specified from –40 °C to +85 °C with 3.3 V ±10% supply.

Key Specifications

Pinout & Package

513FCA001142BAGR uses the Si513 LVDS/LVPECL/HCSL/Dual CMOS pinout configuration with OE on pin 1 and FS on pin 2, housed in a 3.2 × 5.0 mm 6-pin surface-mount package (package code B).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency oscillator applications.

Compared with Si512FCA001142BAGR, 513FCA001142BAGR offers identical timing performance but shifts OE to pin 1 - simplifying routing in compact layouts. Versus Si542AAB001142BAGM, it trades single-frequency precision for essential dual-clock agility in multi-protocol systems.

Availability

513FCA001142BAGR is available at Aetrix Electronics and suitable for PCIe Gen4 root complexes, FPGA configuration subsystems, and SATA III storage controllers requiring stable component supply, short lead times (2–4 weeks), and guaranteed long-term availability.

Supply support for 513FCA001142BAGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and connectivity solutions for high-performance wireless and wired infrastructure.

The Si512/513 family was designed to replace multiple discrete XOs with a single programmable dual-frequency oscillator - targeting FPGA, ASIC, and high-speed serial interface timing in telecom, datacenter, and industrial applications.

FAQ

What are the exact factory-programmed frequencies for 513FCA001142BAGR?

The 513FCA001142BAGR is factory-configured for two precise output frequencies: 100.000000 MHz (selected when FS = 0) and 125.000000 MHz (selected when FS = 1). These values are permanently programmed into the device and cannot be modified in-circuit. Both frequencies are delivered simultaneously on CLK+ and CLK– in LVDS format, with switching latency under 10 ms after FS transition.

Does 513FCA001142BAGR support LVDS termination, and what is the recommended layout?

Yes, 513FCA001142BAGR supports standard LVDS signaling with 100 Ω line-line differential termination. The recommended layout uses matched 50 Ω single-ended traces (100 Ω differential) routed as tightly coupled pairs, terminated at the receiver with a 100 Ω resistor across CLK+ and CLK–. Avoid stubs or vias in the differential path, and maintain solid ground reference beneath the routing to preserve common-mode noise rejection - critical for achieving its specified 0.25 ps RMS phase jitter.

How does the OE pin function on 513FCA001142BAGR, and what happens during disable?

The OE pin (pin 1) on 513FCA001142BAGR is active-high and features internal pull-up. When OE = low, both CLK+ and CLK– outputs enter high-impedance (tri-state) mode with runt suppression - eliminating glitches during power sequencing or dynamic clock gating. Supply current drops to ≤18 mA in this state. OE must remain stable during FS transitions to prevent undefined output states; the datasheet specifies no minimum pulse width, but ≥100 ns is recommended for robust operation.

What is the total stability specification for 513FCA001142BAGR, and what does it include?

The 513FCA001142BAGR has a total stability of ±30 ppm (Grade C), which encompasses initial calibration tolerance, temperature variation (–40 °C to +85 °C), supply voltage change (±10%), load variation, mechanical shock/vibration (non-operational), and 10-year aging at 40 °C. This is not a sum of individual specs but a guaranteed worst-case deviation over the full lifetime and operating range - verified per MIL-STD-883 testing and included in every unit's final production test.

Can 513FCA001142BAGR be used in place of a standard single-output XO?

Yes, 513FCA001142BAGR can operate as a single-output XO by holding the FS pin at a fixed logic level (0 or 1) to select either 100 MHz or 125 MHz continuously. Its LVDS output, ±30 ppm stability, and 0.25 ps RMS phase jitter meet or exceed typical single-output XO specs. However, doing so underutilizes its dual-frequency capability - the primary value lies in dynamic switching between frequencies without external logic or clock multiplexers.