Skyworks Solutions Inc. 515CBA96M0000BAGR

Overview

515CBA96M0000BAGR from Skyworks Solutions is a voltage-controlled crystal oscillator (VCXO) with factory-programmed 96.000 MHz output, ±20 ppm temperature stability, ±120 ppm/V tuning slope, and LVDS output format in a 3.2 × 5.0 mm 6-pin package. It operates from a 3.3 V supply, delivers low jitter (0.25 ps RMS phase jitter, 1.875–20 MHz), and supports telecom clocking in SONET/SDH systems.

For engineers reviewing the 515CBA96M0000BAGR datasheet, 515CBA96M0000BAGR pinout, 515CBA96M0000BAGR application, or 515CBA96M0000BAGR equivalent, this device serves as a high-stability, programmable timing source for FPGA clock generation, PON line cards, and low-jitter PLL reference design where supply noise rejection and control voltage linearity are critical.

Technical Context

The 515CBA96M0000BAGR implements Skyworks' PLL-based frequency synthesis architecture using a fixed AT-cut fundamental-mode crystal, enabling precise 96.000 MHz generation without custom crystals. Its digital control loop provides 1% control voltage linearity and ±10% Kv variation across temperature.

It integrates power supply filtering and supports active-high or active-low OE with internal pull-up/pull-down resistors (45 kΩ). The LVDS output drives 100 Ω differential loads with 0.38 V_PPSE typical swing, 48–52% duty cycle, and <800 ps rise/fall time (20–80% VDD).

Key Specifications

Pinout & Package

Package: 3.2 × 5.0 mm, 6-pin surface-mount ceramic SMD (RoHS-compliant, Pb-free).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar VCXO applications.

Compared with Si514CBA96M0000BAGR and AK2-96.000MHZ-E, the 515CBA96M0000BAGR delivers superior phase noise, tighter stability, and smaller 3.2×5 mm footprint - making it optimal for space-constrained, high-performance telecom and test equipment where jitter and aging directly impact system BER and timing accuracy.

Availability

515CBA96M0000BAGR is available at Aetrix Electronics and suitable for SONET/SDH line cards, PON OLT equipment, and FPGA-based test instrumentation requiring stable component supply with short lead times (<2 weeks).

Supply support for 515CBA96M0000BAGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si515 VCXO product line was designed for high-reliability, any-frequency clock generation in telecom infrastructure, optical networking, and precision instrumentation - replacing custom crystal oscillators with programmable, factory-configured timing modules.

FAQ

What output format and supply voltage does the 515CBA96M0000BAGR use?

The 515CBA96M0000BAGR is configured with LVDS output and a 3.3 V supply, as indicated by the second option code 'B' in its part number. It draws 22–26 mA typical current under load and requires 100 Ω differential termination. This configuration is validated per Skyworks' datasheet Table 1 and ordering guide.

What is the control voltage tuning range and slope for the 515CBA96M0000BAGR?

The 515CBA96M0000BAGR has a control voltage range of 0.1×VDD to 0.9×VDD (0.33–2.97 V at 3.3 V) and a tuning slope of ±120 ppm/V, confirmed in Table 2 of the datasheet. Its control voltage linearity is ±1% BSL, ensuring predictable frequency adjustment across the full tuning range.

Does the 515CBA96M0000BAGR support output enable functionality, and how is it implemented?

Yes, the 515CBA96M0000BAGR includes an OE (output enable) pin (Pin 2) with factory-configured active-high polarity and an internal 45 kΩ pull-up resistor. When OE is low, outputs enter high-impedance state within 5 µs (for f_O ≥10 MHz); when high, full LVDS drive resumes in ≤20 µs.

What is the phase jitter performance of the 515CBA96M0000BAGR at 96 MHz?

While direct 96 MHz phase jitter data is not tabulated, the 515CBA96M0000BAGR inherits the Si515 LVDS jitter profile: 0.25 ps RMS (1.875–20 MHz integration) and 0.8 ps RMS (12 kHz–20 MHz), per Table 6. These values apply to all LVDS frequencies ≥100 MHz, and 96 MHz falls within the validated 74.17582–250 MHz measurement range cited in notes.

Which package footprint does the 515CBA96M0000BAGR use, and what are its dimensions?

The 515CBA96M0000BAGR uses the 3.2 × 5.0 mm 6-pin package (option code 'B'), with nominal body dimensions of 3.2 mm × 5.0 mm × 0.55 mm height. Pin pitch is 1.27 mm, and land pattern recommendations are provided in Skyworks' datasheet Figure 6 and Table 17.