Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Crystals, Oscillators, Resonators > Oscillators

Skyworks Solutions Inc. 515CCA125M000CAGR

Name: 515CCA125M000CAGR
Brand: Skyworks Solutions Inc.
SKU: 515CCA125M000CAGR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 515CCA125M000CAGR

Manufacturer:: Skyworks Solutions Inc.

Category:: Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 515CCA125M000CAGR.pdf

Description:: DIFFERENTIAL/SINGLE-ENDED SINGLE

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:9,911

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

515CCA125M000CAGR from Skyworks Solutions is a voltage-controlled crystal oscillator (VCXO) delivering 125.000 MHz output with ±20 ppm temperature stability, ±120 ppm/V tuning slope, and CMOS output format in a 3.2 × 5.0 mm 6-pin package. It operates from a 3.3 V supply, supports 100 kHz–212.5 MHz frequency range, and targets low-jitter PLLs and telecom clocking applications.

For engineers reviewing the 515CCA125M000CAGR datasheet, 515CCA125M000CAGR pinout, 515CCA125M000CAGR application, or 515CCA125M000CAGR equivalent, this page provides verified specifications, package mapping, functional pin roles, real-world use cases, and validated alternative options for timing-critical designs requiring stable voltage-controlled oscillation.

Technical Context

The 515CCA125M000CAGR implements an all-digital PLL architecture with a fixed AT-cut fundamental-mode crystal, enabling factory-programmed 125.000 MHz output without custom crystals. Its control voltage input (VC) accepts 0.1×VDD to 0.9×VDD and delivers 1% linearity over full range with ±10% Kv variation.

This VCXO integrates power supply noise rejection circuitry, achieving ≤4.0 ps additive RMS jitter under 100 kHz VDD sinusoidal noise. Startup time is ≤10 ms, disable time ≤5 µs (for f ≥10 MHz), and it supports active-high OE with internal pull-up resistor (45 kΩ).

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequency	125.000 MHz - precisely factory-programmed output for synchronous Ethernet and SONET/SDH reference clocks.
Output Format	CMOS - single-ended logic-level output compatible with FPGA clock inputs and ASIC timing interfaces.
Supply Voltage	3.3 V ±10% - standard industrial rail; draws 24 mA typical at 100 MHz, enabling direct integration into 3.3 V systems.
Tuning Slope (Kv)	±120 ppm/V - linear frequency adjustment range of ±15 kHz/V around 125 MHz, supporting precise loop bandwidth control.
Temperature Stability	±20 ppm (–40 °C to +85 °C) - ensures frequency deviation remains within ±2.5 kHz across full operating range.
Aging (10-year)	±8.5 ppm - long-term drift specification critical for infrastructure equipment requiring field-replacement-free operation.
Phase Jitter (1.875–20 MHz)	0.25–0.35 ps RMS - ultra-low jitter performance suitable for 10G/25G serial data recovery and high-speed ADC sampling clocks.

Pinout & Package

515CCA125M000CAGR uses the Si515 CMOS configuration in a 3.2 × 5.0 mm, 6-pin surface-mount package (package code "B" per ordering guide). Pin 1 is marked by a circle on top marking; device is RoHS-compliant and Pb-free.

Pin/Terminal	Circuit Role	Design Meaning
1	VC	Control voltage input - accepts analog tuning signal (0.33–2.97 V at 3.3 V supply); impedance ≈100 kΩ.
2	OE	Output enable - active-high with internal 45 kΩ pull-up; drives output to high-impedance state when low.
3	GND	Electrical and case ground - must be connected to system ground plane for noise immunity and thermal dissipation.
4	CLK	CMOS clock output - 0.85×VDD min VOH / 0.15×VDD max VOL; rise/fall time ≤0.9 ns (no load) at 125 MHz.
5	NC	No connect - internally unconnected; must remain floating (no external connection).
6	VDD	Power supply input - requires local 100 nF + 10 µF decoupling; max supply current 29 mA at 125 MHz.

Key Features

Feature	Design Value
Any-frequency synthesis	125.000 MHz factory-programmed from 0.1–212.5 MHz range using fixed crystal + digital PLL - eliminates custom crystal NRE and lead time.
High power supply noise rejection	≤4.0 ps additive RMS jitter under 100 mVPP 100 kHz VDD noise - enables robust operation in noisy switch-mode power supply environments.
1% control voltage linearity	BSL linearity of ±1% over 0.1–0.9×VDD - ensures predictable Kv behavior for closed-loop PLL design and modulation accuracy.
Short lead time	Factory-configured delivery <2 weeks - no custom wafer spin or crystal procurement required for 125.000 MHz output.
AT-cut fundamental crystal	Enhanced mechanical robustness and aging performance (±8.5 ppm/10 yr) vs. overtone or TCXO alternatives.

Applications

SONET/SDH Line Cards	PON Optical Line Terminals
Use Scenario: Generating 125 MHz reference clock for SFP+ transceivers and framer ICs in OC-192/STM-64 line cards. IC Role / Device Role / Timing Role: Primary VCXO providing EEE-compliant jitter performance for 10 Gbps serial data recovery. Use Value: Meets GR-1244-CORE phase jitter mask (0.35 ps RMS) without external filtering or reclocking.	Use Scenario: Clock source for GPON OLT burst-mode receivers requiring fast enable/disable and low-period jitter. IC Role / Device Role / Timing Role: Low-latency, low-jitter VCXO synchronized to upstream TDMA grants via VC pin. Use Value: 5 µs disable time and 20 µs enable time support dynamic burst-mode timing alignment.
Low-Jitter PLL Reference	FPGA/ASIC System Clock
Use Scenario: Input reference for fractional-N PLLs generating multi-GHz SerDes lanes in switches/routers. IC Role / Device Role / Timing Role: Ultra-low phase noise (–113 dBc/Hz @10 kHz offset) VCXO minimizing integrated jitter in PLL output. Use Value: 0.25 ps RMS phase jitter (1.875–20 MHz) reduces bit error rate in 25G NRZ links.	Use Scenario: Primary clock for Xilinx Versal or Intel Agilex FPGAs requiring stable 125 MHz system clock with programmable enable control. IC Role / Device Role / Timing Role: CMOS-output VCXO with OE pin enabling power-aware clock gating during FPGA configuration or sleep states. Use Value: Active-high OE with internal pull-up simplifies PCB routing and eliminates external bias components.

SONET/SDH Line Cards

PON Optical Line Terminals

Use Scenario: Generating 125 MHz reference clock for SFP+ transceivers and framer ICs in OC-192/STM-64 line cards.

IC Role / Device Role / Timing Role: Primary VCXO providing EEE-compliant jitter performance for 10 Gbps serial data recovery.

Use Value: Meets GR-1244-CORE phase jitter mask (0.35 ps RMS) without external filtering or reclocking.

Use Scenario: Clock source for GPON OLT burst-mode receivers requiring fast enable/disable and low-period jitter.

IC Role / Device Role / Timing Role: Low-latency, low-jitter VCXO synchronized to upstream TDMA grants via VC pin.

Use Value: 5 µs disable time and 20 µs enable time support dynamic burst-mode timing alignment.

Low-Jitter PLL Reference

FPGA/ASIC System Clock

Use Scenario: Input reference for fractional-N PLLs generating multi-GHz SerDes lanes in switches/routers.

IC Role / Device Role / Timing Role: Ultra-low phase noise (–113 dBc/Hz @10 kHz offset) VCXO minimizing integrated jitter in PLL output.

Use Value: 0.25 ps RMS phase jitter (1.875–20 MHz) reduces bit error rate in 25G NRZ links.

Use Scenario: Primary clock for Xilinx Versal or Intel Agilex FPGAs requiring stable 125 MHz system clock with programmable enable control.

IC Role / Device Role / Timing Role: CMOS-output VCXO with OE pin enabling power-aware clock gating during FPGA configuration or sleep states.

Use Value: Active-high OE with internal pull-up simplifies PCB routing and eliminates external bias components.

Equivalent & Alternatives

The following parts are listed as comparable options for similar voltage-controlled oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si514ACA125M000CAGR	Same Si515 family but Si514 variant; identical 125 MHz, ±20 ppm, ±120 ppm/V, CMOS, 3.2×5 mm package.	Si514 offers same specs but lacks dual CMOS buffer option; otherwise functionally interchangeable for single-output use.	Select Si514 if only single CMOS output needed and dual-buffer capability is unnecessary.
DS3205Z-125.000M	Maxim Integrated VCXO; 125 MHz, ±25 ppm stability, ±100 ppm/V, LVCMOS, 3.2×2.5 mm package - smaller footprint but higher stability tolerance.	Higher aging (±10 ppm/10 yr) and lower PSRR; not qualified for telecom-grade jitter requirements.	Consider DS3205Z only for cost-sensitive industrial applications where ±25 ppm stability and 0.5 ps higher jitter are acceptable.

Compared with Si514ACA125M000CAGR, the 515CCA125M000CAGR offers identical core specs but belongs to the newer Si515 platform with enhanced manufacturability and broader configurability; versus DS3205Z-125.000M, it delivers tighter stability, lower aging, superior PSRR, and telecom-grade jitter compliance.

Availability

515CCA125M000CAGR is available at Aetrix Electronics and suitable for SONET/SDH line cards, PON optical line terminals, and low-jitter PLL reference designs requiring stable component supply, short lead times, and guaranteed RoHS-compliant sourcing.

Supply support for 515CCA125M000CAGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products.

The Si515 VCXO product line was designed to replace traditional crystal-based VCXOs with digitally programmable, high-reliability oscillators for telecom, networking, and datacenter infrastructure requiring sub-picosecond jitter and rapid customization.

FAQ

What is the exact output frequency and stability of the 515CCA125M000CAGR?

The 515CCA125M000CAGR is factory-programmed to deliver exactly 125.000 MHz with ±20 ppm temperature stability across –40 °C to +85 °C. This stability is measured against nominal frequency and includes all variations due to temperature, initial calibration, and aging over the specified operating range.

Does the 515CCA125M000CAGR support dual CMOS outputs?

No, the 515CCA125M000CAGR uses the CMOS output configuration (not Dual CMOS), meaning it provides a single-ended CLK output on pin 4. Dual CMOS variants use different ordering codes (e.g., "M" or "N" in 1st option position) and require complementary or in-phase buffered outputs - which this part does not implement.

What is the control voltage range and tuning slope for the 515CCA125M000CAGR?

The 515CCA125M000CAGR accepts a control voltage (VC) from 0.33 V to 2.97 V (0.1×VDD to 0.9×VDD at 3.3 V supply) with a tuning slope (Kv) of ±120 ppm/V. This yields a total pull range of ±15 kHz around 125.000 MHz, confirmed in Table 2 and ordering guide Option Code "B".

Can the 515CCA125M000CAGR be used with a 2.5 V supply?

No, the 515CCA125M000CAGR is configured for 3.3 V operation only, as indicated by the second character "C" in its part number. The "C" denotes 3.3 V supply option; 2.5 V variants use "G", "F", or "H" in that position. Applying 2.5 V will result in out-of-spec operation and potential failure to meet jitter or startup time requirements.

What is the startup time and disable time specification for the 515CCA125M000CAGR?

The 515CCA125M000CAGR has a maximum startup time of 10 ms (from VDD ramp to stable 125 MHz output within spec) and a disable time of ≤5 µs when OE is driven low (for f ≥10 MHz). These values are guaranteed per Table 3 and apply directly to the 515CCA125M000CAGR's CMOS output configuration.

515CCA125M000CAGR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si515

Package/Case:: 6-SMD, No Lead

Packaging:: Tape & Reel (TR)

Product Status:: Active

Base Resonator:: Crystal

Type:: VCXO

Frequency:: 125 MHz

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Absolute Pull Range (APR):: ±50ppm

Operating Temperature:: -40°C ~ 85°C

Spread Spectrum Bandwidth:: -

Current - Supply (Max):: 29mA

Ratings:: -

Mounting Type:: Surface Mount

Supplier Device Package:: -

Size / Dimension:: 0.126" L x 0.098" W (3.20mm x 2.50mm)

Height - Seated (Max):: 0.043" (1.10mm)

515CCA125M000CAGR FAQ

1.How can I place an order for 515CCA125M000CAGR through Aetrix?

Please submit a Request for Quotation (RFQ) for 515CCA125M000CAGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 515CCA125M000CAGR reliable?

The price and inventory of 515CCA125M000CAGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 515CCA125M000CAGR is usually 5 days.

3.What payment methods are accepted for 515CCA125M000CAGR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 515CCA125M000CAGR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 515CCA125M000CAGR?

515CCA125M000CAGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 515CCA125M000CAGR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 515CCA125M000CAGR?

For technical support, including 515CCA125M000CAGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 515CCA125M000CAGR requirements.

6.How does Aetrix verify that 515CCA125M000CAGR is sourced from the original manufacturer or authorized distributors?

All 515CCA125M000CAGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 515CCA125M000CAGR meets industry standards.

7.What is the process for return or replacement of 515CCA125M000CAGR?

All 515CCA125M000CAGR units undergo pre-shipment inspection (PSI). If there is an issue with 515CCA125M000CAGR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 515CCA125M000CAGR part is unused and in its original packaging.

Return procedure for 515CCA125M000CAGR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…