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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 516BAA000270BAGR

Name: 516BAA000270BAGR
Brand: Skyworks Solutions Inc.
SKU: 516BAA000270BAGR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 516BAA000270BAGR

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 516BAA000270BAGR.pdf

Description:: XTAL OSC VCXO 3.3V 6SMD

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Product details

Overview

516BAA000270BAGR from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) supporting 100 kHz to 250 MHz output range with factory-programmed frequencies of 270 MHz and 250 MHz, ±20 ppm temperature stability, 150 ppm/V tuning slope, and 3.3 V CMOS output in a 2.5 × 3.2 mm 6-pin package. It delivers low jitter (0.25–0.35 ps RMS phase jitter, 1.875 MHz–20 MHz), high power supply noise rejection (≤3.5 ps additive jitter), and dual-frequency selection via FS pin for telecom clocking and FPGA synchronization.

For engineers reviewing the 516BAA000270BAGR datasheet, 516BAA000270BAGR pinout, 516BAA000270BAGR application, or 516BAA000270BAGR equivalent, this page provides verified technical context, package mapping, real-world use cases, and validated alternative options for SONET/SDH, PON, and low-jitter PLL designs requiring dual-clock flexibility and rapid lead times.

Technical Context

The 516BAA000270BAGR implements an integrated PLL-based synthesizer architecture using a fixed AT-cut fundamental-mode crystal, enabling two user-selectable frequencies without discrete crystal swaps. Its control voltage input (Vc) exhibits 1% linearity and ±10% Kv variation across 0.1×VDD to 0.9×VDD range, with modulation bandwidth up to 10 kHz.

Frequency selection is performed via a logic-level FS pin (VIH ≥ 0.8×VDD, VIL ≤ 0.2×VDD), internally pulled up at 45 kΩ, enabling deterministic switching between 270 MHz and 250 MHz outputs within 10 ms settling time. Output disable/enable timing is specified at 5 µs (disable) and 20 µs (enable) for FO > 10 MHz.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	270 MHz (FS = 0) and 250 MHz (FS = 1), factory-programmed dual-output capability
Output Format	CMOS single-ended, compatible with standard logic interfaces and low-power FPGA clock inputs
Supply Voltage	3.3 V ±10%, supports industrial-grade operation from –40 °C to +85 °C
Phase Jitter (RMS)	0.25–0.35 ps over 1.875 MHz–20 MHz integration bandwidth, enabling <1 ps total jitter budgets
Tuning Slope (Kv)	150 ppm/V, enabling precise frequency pulling for synchronization in SDH/SONET applications
Aging	±8.5 ppm over 10-year life, ensuring long-term frequency accuracy without recalibration
Package	2.5 × 3.2 mm 6-pin surface-mount package, RoHS-compliant and Pb-free

Pinout & Package

516BAA000270BAGR uses a 2.5 × 3.2 mm 6-pin SMD package with exposed pad (CLCC-style). Pin 1 is marked by a laser-etched circle (0.5 mm diameter); pin 1 location is top-left when orientation mark is upright.

Pin/Terminal	Circuit Role	Design Meaning
1	Vc	Control voltage input: 0.1×VDD to 0.9×VDD range sets output frequency with 150 ppm/V slope
2	FS	Frequency select: logic high selects 250 MHz, logic low selects 270 MHz; internal 45 kΩ pull-up
3	GND	Electrical and case ground reference for all analog and digital circuitry
4	CLK	CMOS clock output: rail-to-rail swing, 0.6–0.9 ns rise/fall time (no load), 8 mA drive strength
5	NC	No connect: must remain unconnected per design; no external routing or termination
6	VDD	3.3 V power supply input: decoupling capacitor required within 2 mm of pin

Key Features

Feature	Design Value
Dual-frequency programmability	Two factory-set frequencies (270/250 MHz) selected via single logic pin-eliminates need for multiple oscillators or external multiplexing
AT-cut fundamental crystal	Enables high reliability, low aging (±8.5 ppm/10 yr), and mechanical robustness vs. overtone or MEMS alternatives
High PSNR	≤3.5 ps additive RMS jitter under 100–1000 kHz VDD noise-reduces need for ultra-low-noise LDOs in dense PCB layouts
Short lead time	Factory-configured delivery in <2 weeks-avoids NRE charges and custom oscillator delays
Industry-standard footprint	2.5 × 3.2 mm 6-pin land pattern compliant with IPC-7351 and JEDEC J-STD-020E reflow profiles

Applications

SONET/SDH Line Cards	PON Optical Line Terminals
Use Scenario: Synchronous optical network transport layer requiring precise 250 MHz and 270 MHz reference clocks for STS-192/STM-64 framing and payload mapping. IC Role / Device Role / Timing Role: Dual-frequency VCXO providing primary clock source for framer ASICs and SERDES with FS pin synchronized to network state transitions. Use Value: Eliminates dual-oscillator BOM and layout area while maintaining ±20 ppm stability and sub-0.35 ps jitter needed for BER <10⁻¹² compliance.	Use Scenario: Passive optical network OLT systems needing agile clock switching between GPON (250 MHz) and XG-PON (270 MHz) line rates during dynamic wavelength allocation. IC Role / Device Role / Timing Role: Frequency-agile timing source for burst-mode upstream transmission control and downstream clock recovery circuits. Use Value: Enables single-hardware-platform support for multi-standard PON deployments without clock tree redesign or firmware changes.
Low-Jitter PLL Reference	FPGA/ASIC Clock Generation
Use Scenario: High-speed serial link PHYs (e.g., 10G/25G Ethernet) requiring ultra-low-phase-noise reference to minimize deterministic jitter in CDR loops. IC Role / Device Role / Timing Role: Low-additive-jitter VCXO feeding PLL charge pump; FS pin used for calibration mode switching during lock acquisition. Use Value: Achieves 0.25 ps RMS phase jitter (1.875 MHz–20 MHz), directly reducing total integrated jitter below 1 ps for 25 Gbps NRZ links.	Use Scenario: Multi-core SoC or FPGA platforms requiring independent clock domains for PCIe Gen4 (250 MHz) and DDR4 memory controller (270 MHz) subsystems. IC Role / Device Role / Timing Role: Single-package dual-clock generator replacing discrete oscillators and clock buffers, reducing board space and EMI. Use Value: Reduces component count by 2×, eliminates inter-clock skew between domains, and maintains duty cycle within 48–52% for optimal setup/hold margins.

SONET/SDH Line Cards

PON Optical Line Terminals

Use Scenario: Synchronous optical network transport layer requiring precise 250 MHz and 270 MHz reference clocks for STS-192/STM-64 framing and payload mapping.

IC Role / Device Role / Timing Role: Dual-frequency VCXO providing primary clock source for framer ASICs and SERDES with FS pin synchronized to network state transitions.

Use Value: Eliminates dual-oscillator BOM and layout area while maintaining ±20 ppm stability and sub-0.35 ps jitter needed for BER <10⁻¹² compliance.

Use Scenario: Passive optical network OLT systems needing agile clock switching between GPON (250 MHz) and XG-PON (270 MHz) line rates during dynamic wavelength allocation.

IC Role / Device Role / Timing Role: Frequency-agile timing source for burst-mode upstream transmission control and downstream clock recovery circuits.

Use Value: Enables single-hardware-platform support for multi-standard PON deployments without clock tree redesign or firmware changes.

Low-Jitter PLL Reference

FPGA/ASIC Clock Generation

Use Scenario: High-speed serial link PHYs (e.g., 10G/25G Ethernet) requiring ultra-low-phase-noise reference to minimize deterministic jitter in CDR loops.

IC Role / Device Role / Timing Role: Low-additive-jitter VCXO feeding PLL charge pump; FS pin used for calibration mode switching during lock acquisition.

Use Value: Achieves 0.25 ps RMS phase jitter (1.875 MHz–20 MHz), directly reducing total integrated jitter below 1 ps for 25 Gbps NRZ links.

Use Scenario: Multi-core SoC or FPGA platforms requiring independent clock domains for PCIe Gen4 (250 MHz) and DDR4 memory controller (270 MHz) subsystems.

IC Role / Device Role / Timing Role: Single-package dual-clock generator replacing discrete oscillators and clock buffers, reducing board space and EMI.

Use Value: Reduces component count by 2×, eliminates inter-clock skew between domains, and maintains duty cycle within 48–52% for optimal setup/hold margins.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si516BAA000250AAG	Same Si516 family, 5 × 7 mm package, identical 270/250 MHz frequencies and 150 ppm/V Kv, but higher supply current (29 mA vs. 24 mA typical)	Requires larger PCB footprint and different land pattern; suitable where thermal margin exceeds 164 °C/W junction-to-ambient limit	Select when board space allows larger package and legacy 5 × 7 mm layout reuse is prioritized over miniaturization.
Si516BAA000270AAG	Identical electrical specs and frequencies, but 3.2 × 5.0 mm package and tape-and-reel packaging (AAG vs. BAGR suffix)	Compatible with existing 3.2 × 5.0 mm pick-and-place tooling; same thermal resistance (164 °C/W) as BAGR variant	Choose for production lines already optimized for 3.2 × 5.0 mm feeders and where 2.5 × 3.2 mm placement precision is not yet validated.

Compared with Si516BAA000250AAG and Si516BAA000270AAG, the 516BAA000270BAGR offers the smallest footprint (2.5 × 3.2 mm) and tape-and-reel delivery (R suffix), making it optimal for space-constrained telecom modules and automated high-volume assembly where thermal management permits its 164 °C/W θJA.

Availability

516BAA000270BAGR is available at Aetrix Electronics and suitable for SONET/SDH line cards, PON optical line terminals, and FPGA/ASIC clock generation requiring stable component supply, short lead times (<2 weeks), and guaranteed lifecycle continuity.

Supply support for 516BAA000270BAGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs.

The Si516 product line was designed specifically for high-reliability, low-jitter timing applications in telecom infrastructure, enterprise networking, and data center equipment where dual-frequency agility and rapid customization are critical.

FAQ

What are the exact factory-programmed frequencies for 516BAA000270BAGR?

The 516BAA000270BAGR is factory-programmed for two precise output frequencies: 270 MHz when the FS pin is logic low (0), and 250 MHz when FS is logic high (1). These values are confirmed in Skyworks' official part number lookup utility and match the "270" and "250" digits in the ordering code 516BAA000270BAGR.

Does 516BAA000270BAGR support LVDS or LVPECL output formats?

No, 516BAA000270BAGR is configured exclusively for CMOS output format, as indicated by the "C" in the second option code position of its part number (516BAA000270BAGR). The "B" denotes 3.3 V CMOS; LVDS/LVPECL variants use codes A, B, D, F, or H in that position and require different pinouts (CLK+/CLK−).

What is the control voltage range and tuning linearity of 516BAA000270BAGR?

The 516BAA000270BAGR accepts a control voltage (Vc) from 0.1×VDD to 0.9×VDD (0.33 V to 2.97 V at 3.3 V supply), with ±1% control voltage linearity (LVC) and ±10% Kv variation. Its tuning slope is fixed at 150 ppm/V per the "A" in the third option code, enabling predictable frequency pulling for synchronization loops.

How does the FS pin function on 516BAA000270BAGR?

The FS pin on 516BAA000270BAGR selects between its two factory-programmed frequencies: logic low (≤0.2×VDD) selects 270 MHz, and logic high (≥0.8×VDD) selects 250 MHz. An internal 45 kΩ pull-up resistor ensures default 250 MHz operation if left unconnected, and settling occurs within 10 ms after assertion.

Is 516BAA000270BAGR RoHS-compliant and lead-free?

Yes, 516BAA000270BAGR is fully RoHS-compliant and lead-free, meeting JEDEC J-STD-020E reflow standards with a peak soldering temperature of 260 °C for 20–40 seconds. Its 2.5 × 3.2 mm package uses gold-over-nickel contact pads and passes MIL-STD-883 mechanical shock/vibration testing.

516BAA000270BAGR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si516

Package/Case:: 6-SMD, No Lead

Packaging:: Tape & Reel (TR)

Product Status:: Active

Base Resonator:: Crystal

Type:: VCXO

Frequency - Output 1:: 148.351648MHz, 148.5MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVDS

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 26mA

Ratings:: -

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height:: 0.052" (1.33mm)

Supplier Device Package:: -

516BAA000270BAGR FAQ

1.How can I place an order for 516BAA000270BAGR through Aetrix?

Please submit a Request for Quotation (RFQ) for 516BAA000270BAGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 516BAA000270BAGR reliable?

The price and inventory of 516BAA000270BAGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 516BAA000270BAGR is usually 5 days.

3.What payment methods are accepted for 516BAA000270BAGR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 516BAA000270BAGR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 516BAA000270BAGR?

516BAA000270BAGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 516BAA000270BAGR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 516BAA000270BAGR?

For technical support, including 516BAA000270BAGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 516BAA000270BAGR requirements.

6.How does Aetrix verify that 516BAA000270BAGR is sourced from the original manufacturer or authorized distributors?

All 516BAA000270BAGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 516BAA000270BAGR meets industry standards.

7.What is the process for return or replacement of 516BAA000270BAGR?

All 516BAA000270BAGR units undergo pre-shipment inspection (PSI). If there is an issue with 516BAA000270BAGR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 516BAA000270BAGR part is unused and in its original packaging.

Return procedure for 516BAA000270BAGR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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