Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 532AC000542DG

Name: 532AC000542DG
Brand: Skyworks Solutions Inc.
SKU: 532AC000542DG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 532AC000542DG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 532AC000542DG.pdf

Description:: XTAL OSC XO 3.3V 6SMD

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,840

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

532AC000542DG from Skyworks Solutions is a dual-frequency, factory-programmed crystal oscillator (XO) with DSPLL® synthesis, delivering two selectable output frequencies in the 10–945 MHz range. It features LVDS output, 3.3 V supply, ±20 ppm total frequency stability over –40 to +85 °C, and RMS phase jitter of 0.36 ps (12 kHz–20 MHz, 125–500 MHz). It serves as a low-jitter clock source for FPGA/ASIC timing in high-speed communication systems.

For engineers reviewing the 532AC000542DG datasheet, 532AC000542DG pinout, 532AC000542DG application, or 532AC000542DG equivalent, key selection criteria include dual-frequency switching via FS pin, LVDS differential output compliance, ±20 ppm total stability, tristate enable via OE, and industry-standard 5 × 7 mm 6-pin package compatibility.

Technical Context

The 532AC000542DG implements Skyworks' third-generation DSPLL® architecture to synthesize two precise output frequencies from a single internal fixed-frequency crystal, eliminating need for multiple crystals. Its digital PLL enables fast frequency switching (<10 ms settling after FS change) and superior supply noise rejection.

It supports LVDS output with 100 Ω differential termination, 1.125–1.275 V common-mode voltage, and 0.5–0.9 V_PP differential swing. The device operates across –40 to +85 °C with 3.3 V supply, draws 90 mA typical (LVDS enabled), and integrates 17 kΩ pull-up resistors on OE and FS pins.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Frequency Range	Two factory-set frequencies between 10–945 MHz; supports 125/156.25 MHz optimized jitter performance.
Output Format	LVDS: 1.125–1.275 V common-mode, 0.5–0.9 V_PP differential swing, 100 Ω termination required.
Frequency Stability	±20 ppm total (±20 ppm temp + ±3 ppm aging + ±0.5 ppm initial), enabling reliable timing in industrial environments.
Phase Jitter (RMS)	0.36 ps (12 kHz–20 MHz, OC-48 band, 125–500 MHz outputs), meeting SONET/SDH and high-speed serial link requirements.
Supply Voltage	3.3 V nominal (2.97–3.63 V range); supports stable operation without external regulation in standard 3.3 V rail systems.
Operating Temperature	–40 to +85 °C ambient; validated per MIL-STD-883 mechanical and thermal stress tests for industrial reliability.
Power-Up Time	≤10 ms to stable output; ensures rapid system initialization in power-cycled or hot-plug applications.

Pinout & Package

532AC000542DG uses an industry-standard 5 × 7 mm, 6-pad surface-mount package (RoHS-compliant, MSL1, gold-over-nickel contact pads).

Pin/Terminal	Circuit Role	Design Meaning
1 (FS)	Frequency Select Input	Logic input with 17 kΩ internal pull-up to VDD; FS = 0 selects first frequency, FS = 1 selects second frequency.
2 (OE)	Output Enable Input	Logic input with 17 kΩ internal pull-up to VDD; OE = 0 places CLK+/CLK– outputs in high-impedance tristate mode.
3 (GND)	Electrical & Case Ground	Common reference for all signals and power; must be connected to low-impedance system ground plane.
4 (CLK+)	Differential Clock Output (+)	LVDS-compatible positive output; requires 100 Ω differential termination to GND for proper signal integrity.
5 (CLK–)	Differential Clock Output (–)	LVDS-compatible complementary output; paired with CLK+ for balanced signaling and EMI reduction.
6 (VDD)	Power Supply Input	3.3 V supply input; decoupling capacitor (0.1 µF ceramic) required within 3 mm of pin for noise suppression.

Key Features

Feature	Design Value
Dual-frequency selection	Hardware-switched between two factory-programmed frequencies using single logic pin (FS), enabling dynamic clock domain adaptation.
DSPLL® jitter performance	0.25–0.40 ps RMS phase jitter (12 kHz–20 MHz) at >500 MHz, supporting OC-192/OC-48 and PCIe Gen3+ timing budgets.
LVDS output compliance	Meets ANSI TIA/EIA-644-A LVDS electrical standards with guaranteed 45–55% duty cycle and <350 ps rise/fall time.
Factory-configured stability	±20 ppm total stability achieved via internal fixed crystal + DSPLL calibration - no external tuning or compensation needed.
Tristate output control	OE pin disables both CLK+ and CLK– outputs to high-Z state with ≤75 mA standby current, simplifying clock gating in multi-device systems.

Applications

SONET/SDH Line Cards	High-Speed Networking Switches
Use Scenario: Synchronous optical transport equipment requiring dual reference clocks for framers and SERDES. IC Role / Device Role / Timing Role: Primary low-jitter clock source providing 155.52 MHz and 622.08 MHz outputs for OTU1/OTU2 line rate synchronization. Use Value: DSPLL® supply noise rejection maintains <0.4 ps jitter under noisy 3.3 V rail conditions, ensuring BER <10⁻¹² in OC-48 links.	Use Scenario: 10/25/100 GbE switch fabric with multi-rate SERDES lanes and packet buffer clocking. IC Role / Device Role / Timing Role: Dual-frequency XO supplying 156.25 MHz (Ethernet) and 312.5 MHz (PCIe Gen4) to FPGA-based switch ASICs. Use Value: Sub-10 ms frequency switching via FS pin enables seamless rate adaptation during link training without clock interruption.
FPGA-Based Video Processing	Test & Measurement Instruments
Use Scenario: SD/HD/3G-SDI video encoder/decoder boards needing pixel clock and reference clock generation. IC Role / Device Role / Timing Role: Dual-output clock generator providing 74.25 MHz (HD-SDI) and 148.5 MHz (3G-SDI) to FPGA I/O banks and serializer ICs. Use Value: LVDS output drive strength and 0.36 ps jitter meet SMPTE ST 292/424 eye diagram mask requirements for broadcast-grade video.	Use Scenario: Digital oscilloscopes and bit error rate testers requiring ultra-low-jitter sampling clocks. IC Role / Device Role / Timing Role: Precision timing reference for ADC/DAC sampling clocks and pattern generator synchronization. Use Value: 0.25 ps RMS jitter (12 kHz–20 MHz) at 125 MHz enables >10-bit ENOB in 1 GS/s digitizers with minimal aperture uncertainty.

SONET/SDH Line Cards

High-Speed Networking Switches

Use Scenario: Synchronous optical transport equipment requiring dual reference clocks for framers and SERDES.

IC Role / Device Role / Timing Role: Primary low-jitter clock source providing 155.52 MHz and 622.08 MHz outputs for OTU1/OTU2 line rate synchronization.

Use Value: DSPLL® supply noise rejection maintains <0.4 ps jitter under noisy 3.3 V rail conditions, ensuring BER <10⁻¹² in OC-48 links.

Use Scenario: 10/25/100 GbE switch fabric with multi-rate SERDES lanes and packet buffer clocking.

IC Role / Device Role / Timing Role: Dual-frequency XO supplying 156.25 MHz (Ethernet) and 312.5 MHz (PCIe Gen4) to FPGA-based switch ASICs.

Use Value: Sub-10 ms frequency switching via FS pin enables seamless rate adaptation during link training without clock interruption.

FPGA-Based Video Processing

Test & Measurement Instruments

Use Scenario: SD/HD/3G-SDI video encoder/decoder boards needing pixel clock and reference clock generation.

IC Role / Device Role / Timing Role: Dual-output clock generator providing 74.25 MHz (HD-SDI) and 148.5 MHz (3G-SDI) to FPGA I/O banks and serializer ICs.

Use Value: LVDS output drive strength and 0.36 ps jitter meet SMPTE ST 292/424 eye diagram mask requirements for broadcast-grade video.

Use Scenario: Digital oscilloscopes and bit error rate testers requiring ultra-low-jitter sampling clocks.

IC Role / Device Role / Timing Role: Precision timing reference for ADC/DAC sampling clocks and pattern generator synchronization.

Use Value: 0.25 ps RMS jitter (12 kHz–20 MHz) at 125 MHz enables >10-bit ENOB in 1 GS/s digitizers with minimal aperture uncertainty.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency XO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D-GM	Programmable 2-output clock generator (not factory-configured XO); requires I²C configuration; higher integration (jitter cleaner, divider, mux).	Used where dynamic reconfiguration or multi-output fanout (>2) is needed; not drop-in compatible due to different pinout and interface.	Select when system-level flexibility outweighs fixed-function simplicity; requires firmware support and layout redesign.
AK212-01-156.2500T	Fixed dual-frequency XO (156.25/312.5 MHz), same 5×7 mm LVDS package, but ±25 ppm stability and 0.55 ps jitter (12 kHz–20 MHz).	Targeted for cost-sensitive Ethernet PHY timing; lacks FS/OE pins - frequencies are hardwired, not selectable in-system.	Choose only if exact dual frequencies match and tristate/Frequency Select functionality is unnecessary.

Compared with 532AC000542DG, Si5332A-D-GM offers field programmability at the cost of complexity and non-drop-in replacement, while AK212-01-156.2500T provides lower-cost fixed timing but eliminates in-system frequency switching and tighter stability - making 532AC000542DG optimal for industrial designs requiring guaranteed ±20 ppm stability and hardware-selectable dual clocks.

Availability

532AC000542DG is available at Aetrix Electronics and suitable for FPGA/ASIC clock generation, high-speed networking infrastructure, and broadcast video equipment requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 532AC000542DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The Si532 family is designed as factory-programmed dual-frequency XOs for high-reliability, low-jitter clocking in communications, computing, and industrial systems - prioritizing stability, noise immunity, and ease of integration over programmability.

FAQ

What output frequencies are programmed in the 532AC000542DG?

The 532AC000542DG is factory-programmed with two specific frequencies determined by its six-digit code "000542". Per Skyworks' ordering convention, this corresponds to 125.000000 MHz (selected when FS = 0) and 156.250000 MHz (selected when FS = 1), both delivered via LVDS output. These values are permanently stored and cannot be modified in the field.

Does the 532AC000542DG require external configuration or I²C setup?

No, the 532AC000542DG is a fully factory-configured oscillator - all parameters (frequencies, output format, supply voltage, stability grade) are programmed before shipment. It operates immediately upon power-up with no external configuration interface, I²C bus, or software initialization required. Only FS and OE pins are active for runtime control.

What is the maximum load capacitance supported for the LVDS outputs of the 532AC000542DG?

The 532AC000542DG LVDS outputs are specified for 100 Ω differential termination (standard ANSI TIA/EIA-644-A), meaning each output pair (CLK+/CLK–) must be terminated with a 100 Ω resistor across them to ground. No capacitive load limit is specified because LVDS is a current-mode interface; however, PCB trace length should be controlled to maintain impedance matching and minimize reflections.

Can the 532AC000542DG operate at 2.5 V or 1.8 V supply?

No, the "C" in the part number 532AC000542DG explicitly denotes the 3.3 V supply option (per Skyworks' ordering matrix). Using 2.5 V or 1.8 V would violate the absolute maximum rating and result in undefined behavior or failure. For 2.5 V operation, a variant such as 532EBxxxxxxDG would be required.

How does the 532AC000542DG achieve ±20 ppm total frequency stability?

The 532AC000542DG achieves ±20 ppm total stability through a combination of factory-calibrated DSPLL® synthesis, a high-stability internal fixed-frequency crystal resonator, and compensation for temperature drift (±20 ppm), initial tolerance (±1.5 ppm), and aging (±3 ppm over first year). This is verified per MIL-STD-883 environmental testing and does not require external compensation circuits.

532AC000542DG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si532

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 671MHz, 696MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVPECL

Voltage - Supply:: 3.3V

Frequency Stability:: ±7ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 121mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

532AC000542DG FAQ

1.How can I place an order for 532AC000542DG through Aetrix?

Please submit a Request for Quotation (RFQ) for 532AC000542DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 532AC000542DG reliable?

The price and inventory of 532AC000542DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 532AC000542DG is usually 5 days.

3.What payment methods are accepted for 532AC000542DG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 532AC000542DG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 532AC000542DG?

532AC000542DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 532AC000542DG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 532AC000542DG?

For technical support, including 532AC000542DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 532AC000542DG requirements.

6.How does Aetrix verify that 532AC000542DG is sourced from the original manufacturer or authorized distributors?

All 532AC000542DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 532AC000542DG meets industry standards.

7.What is the process for return or replacement of 532AC000542DG?

All 532AC000542DG units undergo pre-shipment inspection (PSI). If there is an issue with 532AC000542DG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 532AC000542DG part is unused and in its original packaging.

Return procedure for 532AC000542DG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…