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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 532BB000594DG

Name: 532BB000594DG
Brand: Skyworks Solutions Inc.
SKU: 532BB000594DG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 532BB000594DG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 532BB000594DG.pdf

Description:: XTAL OSC XO 3.3V 6SMD

Quantity:: RFQ Add To RFQ list

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Inventory:4,814

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Product details

Overview

532BB000594DG from Skyworks Solutions is a dual-frequency, factory-programmed crystal oscillator (XO) with DSPLL® synthesis, delivering two selectable output frequencies in the 10–945 MHz range. It features LVDS output, 2.5 V supply, ±20 ppm total frequency stability over –40 to +85 °C, and ultra-low phase jitter of 0.36 ps RMS (12 kHz–20 MHz, OC-48). It serves as a timing source for FPGA clock generation and high-speed serial interfaces.

For engineers reviewing the 532BB000594DG datasheet, 532BB000594DG pinout, 532BB000594DG application, or 532BB000594DG equivalent, key selection criteria include dual-frequency switching via FS pin, LVDS drive capability at 2.5 V, ±20 ppm total stability, and compatibility with industry-standard 5 × 7 mm 6-pin surface-mount footprint.

Technical Context

The 532BB000594DG implements Skyworks' third-generation DSPLL® architecture to synthesize two precise output frequencies from a single internal fixed-crystal reference. Its dual-frequency selection is controlled by the FS pin, enabling real-time switching between preprogrammed f₀ and f₁ without reconfiguration delay.

It supports LVDS differential signaling with 100 Ω termination, delivers 0.7 VPP typical differential swing, and achieves 45–55% duty cycle symmetry. Power-up time is ≤10 ms, and frequency settling after FS transition is ≤10 ms - critical for dynamic clock domain switching in telecom and datacom systems.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequency	Two factory-set frequencies in 10–945 MHz range; exact values encoded in "000594" part number identifier
Output Format	LVDS - requires 100 Ω differential termination; compatible with standard FPGA/ASIC clock inputs
Supply Voltage	2.5 V ±0.25 V - enables low-noise operation with reduced power vs. 3.3 V options
Total Frequency Stability	±31.5 ppm - includes ±20 ppm temperature stability + ±10 ppm aging over 20 years
Phase Jitter (RMS)	0.36 ps (12 kHz–20 MHz, OC-48) - meets SONET/SDH and PCIe Gen3 timing budgets
Operating Temperature	–40 to +85 °C - qualified per MIL-STD-883 for industrial and networking environments
Package	5 × 7 mm, 6-pad surface-mount - industry-standard footprint with pin-compatible replacement path

Pinout & Package

532BB000594DG uses a RoHS-compliant, 6-pad, 5 × 7 mm surface-mount package with exposed pad thermal enhancement. Pin 1 is marked by a dot; orientation follows standard top-view layout.

Pin/Terminal	Circuit Role	Design Meaning
1 (FS)	Frequency Select Input	Logic-level control: FS = 0 selects first frequency; FS = 1 selects second frequency; internal 17 kΩ pullup to VDD
2 (OE)	Output Enable Input	Active-high enable: OE = 0 tristates CLK+/CLK− outputs; OE = 1 enables LVDS output; internal 17 kΩ pullup
3 (GND)	Ground Reference	Common return for power and signal; must be connected to low-impedance system ground plane
4 (CLK+)	Differential Output Positive	LVDS output terminal; requires 100 Ω differential termination to GND for proper common-mode voltage (1.2 V)
5 (CLK−)	Differential Output Negative	LVDS complementary output; paired with CLK+; unused in CMOS variants but functional here
6 (VDD)	Power Supply	2.5 V supply input; bypassing with 0.1 µF ceramic capacitor near pin is mandatory for jitter performance

Key Features

Feature	Design Value
Dual-frequency selection	Hardware-switched between two factory-programmed frequencies via single FS pin - eliminates need for external configuration logic
DSPLL® jitter suppression	0.36 ps RMS phase jitter enables use in 10G Ethernet and OTN clock recovery where sub-0.5 ps is required
Fixed internal crystal	Eliminates crystal aging variability and board-level tuning; ensures ±3 ppm first-year aging and ±10 ppm 20-year drift
LVDS output compliance	Meets JEDEC JESD8-12 standards: 1.125–1.275 V common-mode, 0.5–0.9 VPP differential swing, <350 ps rise/fall
Supply noise rejection	Superior PSRR from DSPLL architecture allows stable operation in noisy 2.5 V rail environments without dedicated LDO

Applications

SONET/SDH Line Cards	High-Speed FPGA Prototyping
Use Scenario: Synchronous optical network line cards requiring dual-reference clocks for OC-48 and OC-192 framing layers. IC Role / Device Role / Timing Role: Primary clock source providing two low-jitter references - one for SERDES PLL lock, another for system management bus timing. Use Value: Enables seamless layer switching without clock interruption; ±31.5 ppm stability ensures frame alignment across temperature extremes.	Use Scenario: Rapid FPGA-based protocol validation platforms needing flexible clock sources for multiple I/O standards (PCIe, DDR4, HDMI). IC Role / Device Role / Timing Role: Dual-frequency clock generator allowing on-the-fly clock domain selection during test mode transitions. Use Value: Reduces need for multiple oscillators or programmable clock chips; FS pin toggling provides deterministic, sub-10 ms frequency change.
Test Equipment Clock Synthesis	HD Video Timing Generator
Use Scenario: Automated test equipment requiring precise, switchable clock stimuli for jitter tolerance testing of SerDes receivers. IC Role / Device Role / Timing Role: Stimulus clock generator with calibrated phase noise profile matching OC-192 and 10GBASE-R masks. Use Value: 0.34 ps RMS jitter (50 kHz–80 MHz) satisfies IEEE 802.3ae test requirements without external cleanup PLL.	Use Scenario: Broadcast-grade HD video encoders needing stable pixel clock (e.g., 74.25 MHz) and audio sample clock (e.g., 48 MHz) simultaneously. IC Role / Device Role / Timing Role: Dual-output timing reference replacing discrete XO pair; FS pin selects between video and audio domains. Use Value: Eliminates inter-clock skew; LVDS outputs drive long traces with minimal EMI, supporting 1080p60 timing integrity.

SONET/SDH Line Cards

High-Speed FPGA Prototyping

Use Scenario: Synchronous optical network line cards requiring dual-reference clocks for OC-48 and OC-192 framing layers.

IC Role / Device Role / Timing Role: Primary clock source providing two low-jitter references - one for SERDES PLL lock, another for system management bus timing.

Use Value: Enables seamless layer switching without clock interruption; ±31.5 ppm stability ensures frame alignment across temperature extremes.

Use Scenario: Rapid FPGA-based protocol validation platforms needing flexible clock sources for multiple I/O standards (PCIe, DDR4, HDMI).

IC Role / Device Role / Timing Role: Dual-frequency clock generator allowing on-the-fly clock domain selection during test mode transitions.

Use Value: Reduces need for multiple oscillators or programmable clock chips; FS pin toggling provides deterministic, sub-10 ms frequency change.

Test Equipment Clock Synthesis

HD Video Timing Generator

Use Scenario: Automated test equipment requiring precise, switchable clock stimuli for jitter tolerance testing of SerDes receivers.

IC Role / Device Role / Timing Role: Stimulus clock generator with calibrated phase noise profile matching OC-192 and 10GBASE-R masks.

Use Value: 0.34 ps RMS jitter (50 kHz–80 MHz) satisfies IEEE 802.3ae test requirements without external cleanup PLL.

Use Scenario: Broadcast-grade HD video encoders needing stable pixel clock (e.g., 74.25 MHz) and audio sample clock (e.g., 48 MHz) simultaneously.

IC Role / Device Role / Timing Role: Dual-output timing reference replacing discrete XO pair; FS pin selects between video and audio domains.

Use Value: Eliminates inter-clock skew; LVDS outputs drive long traces with minimal EMI, supporting 1080p60 timing integrity.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency XO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5332A-D-GM	Programmable multi-output clock generator (not factory-configured XO); requires I²C setup; higher integration but larger 4 × 4 mm QFN	Used when >2 outputs or frequency agility beyond two points is needed; not drop-in for fixed dual-XO role	Select only if design requires runtime reconfiguration or additional outputs; adds firmware overhead and layout complexity
AK20E-25.000MHZ-T	Single-output LVDS XO at fixed 25 MHz; no FS pin; ±20 ppm stability; same 5 × 7 mm package but 6-pin variant differs in pin function mapping	Applicable only for static single-frequency use cases; lacks dual-frequency switching capability entirely	Choose only when dual-frequency functionality is unnecessary and cost sensitivity outweighs feature set

Compared with Si5332A-D-GM and AK20E-25.000MHZ-T, the 532BB000594DG offers hardware-selectable dual frequencies in a simple, pin-defined interface - ideal for deterministic, low-latency clock switching without software intervention or layout redesign.

Availability

532BB000594DG is available at Aetrix Electronics and suitable for FPGA clock generation, SONET/SDH line cards, and HD video timing applications requiring stable component supply, guaranteed long-term sourcing, and full traceability.

Supply support for 532BB000594DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products.

The Si532 family is designed specifically for high-reliability, low-jitter timing in communications infrastructure - emphasizing factory-configurable dual-frequency XOs that replace custom crystal solutions while maintaining quartz-level stability.

FAQ

What output frequencies are programmed into the 532BB000594DG?

The "000594" suffix in 532BB000594DG corresponds to a specific dual-frequency configuration defined in Skyworks' part numbering system. Per the datasheet, six-digit codes > 000100 indicate the lower frequency is selected when FS = 0 and the higher when FS = 1. Exact f₀ and f₁ values are determined by Skyworks' configuration tool and documented in the device's shipping certificate - not derivable from the part number alone without lookup.

Does the 532BB000594DG support CMOS output?

No, the 532BB000594DG does not support CMOS output. The "B" in the second option code position of the part number (532BB000594DG) specifies LVDS output format. CMOS is only available in variants with option codes C, G, J, P, T, or V - all of which differ in the second character and are limited to ≤160 MHz.

Can the 532BB000594DG operate from a 3.3 V supply?

No, the 532BB000594DG is configured for 2.5 V operation. The second option code "B" maps to 2.5 V supply per the ordering table. Using 3.3 V would exceed the absolute maximum rating for the 2.5 V option (VDD max = 2.75 V) and risk permanent damage. A 3.3 V variant would use option code A, E, or M instead.

Is the 532BB000594DG pin-compatible with other Si532 variants?

Yes, all Si532 devices - including 532BB000594DG - share identical 5 × 7 mm, 6-pin package dimensions and pinout (FS, OE, GND, CLK+, CLK−, VDD), regardless of supply voltage, output format, or stability grade. This enables direct PCB footprint reuse across the family when design constraints allow electrical compatibility.

What is the meaning of "Total Stability ±31.5 ppm" for the 532BB000594DG?

"Total Stability ±31.5 ppm" for the 532BB000594DG combines ±20 ppm temperature stability (over –40 to +85 °C) and ±10 ppm aging over 20 years, plus initial calibration tolerance. It represents the worst-case frequency deviation expected across lifetime and temperature - a key spec for synchronization-critical systems like telecom base stations where long-term holdover accuracy matters.

532BB000594DG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si532

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 125MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVDS

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 98mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

532BB000594DG FAQ

1.How can I place an order for 532BB000594DG through Aetrix?

Please submit a Request for Quotation (RFQ) for 532BB000594DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 532BB000594DG reliable?

The price and inventory of 532BB000594DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 532BB000594DG is usually 5 days.

3.What payment methods are accepted for 532BB000594DG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 532BB000594DG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 532BB000594DG?

532BB000594DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 532BB000594DG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 532BB000594DG?

For technical support, including 532BB000594DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 532BB000594DG requirements.

6.How does Aetrix verify that 532BB000594DG is sourced from the original manufacturer or authorized distributors?

All 532BB000594DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 532BB000594DG meets industry standards.

7.What is the process for return or replacement of 532BB000594DG?

All 532BB000594DG units undergo pre-shipment inspection (PSI). If there is an issue with 532BB000594DG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 532BB000594DG part is unused and in its original packaging.

Return procedure for 532BB000594DG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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