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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 533BC001080DG

Name: 533BC001080DG
Brand: Skyworks Solutions Inc.
SKU: 533BC001080DG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 533BC001080DG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 533BC001080DG.pdf

Description:: XTAL OSCILLATOR

Quantity:: RFQ Add To RFQ list

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Product details

Overview

533BC001080DG from Skyworks Solutions is a dual-frequency, factory-programmed crystal oscillator (XO) with DSPLL® synthesis, delivering two user-specified output frequencies between 10 MHz and 945 MHz (CMOS up to 160 MHz), ±7 ppm temperature stability, 3.3 V supply, and LVDS output in a 5 × 7 mm 6-pin package. It serves as a low-jitter clock source for FPGA/ASIC timing and SD/HD video systems.

For engineers reviewing the 533BC001080DG datasheet, 533BC001080DG pinout, 533BC001080DG application, or 533BC001080DG equivalent, this page provides verified technical context, pin-level design meaning, real-world use cases, and validated alternative options for timing-critical embedded and communications designs.

Technical Context

The 533BC001080DG implements Skyworks' third-generation DSPLL® architecture to synthesize two precise output frequencies from a single internal fixed-frequency crystal, eliminating frequency-specific crystals while maintaining ±7 ppm total stability over –40 to +85 °C. Its dual-frequency selection is controlled via the FS pin, enabling dynamic switching between preprogrammed f₀ and f₁.

It supports LVDS differential outputs with 0.5–0.9 VPP swing, 45–55% duty cycle symmetry, and RMS phase jitter as low as 0.36 ps (12 kHz–20 MHz, 125–500 MHz range). OE pin enables tristate control with internal 17 kΩ pull-up to VDD, and power-up time is ≤10 ms.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequency	Two factory-programmed frequencies within 10–945 MHz (CMOS limited to 160 MHz)
Temperature Stability	±7 ppm over –40 to +85 °C - enables stable operation in industrial-grade environments without external compensation
Output Format	LVDS - differential signaling with 100 Ω termination, 1.125–1.275 V common-mode, 0.5–0.9 VPP swing
Supply Voltage	3.3 V (2.97–3.63 V operating range) - compatible with standard logic rails and noise-tolerant DSPLL regulation
Phase Jitter (RMS)	0.36 ps typical (12 kHz–20 MHz, 125–500 MHz) - meets OC-48/SONET timing requirements
Initial Accuracy	±1.5 ppm at +25 °C - ensures tight frequency alignment at power-on before thermal stabilization
Aging (20-year)	±10 ppm - guarantees long-term frequency integrity in deployed infrastructure equipment

Pinout & Package

533BC001080DG uses an industry-standard 5 × 7 mm, 6-pad surface-mount package (RoHS-compliant, MSL1, gold-over-nickel contact pads). Pin layout follows Skyworks' standardized top-view orientation with Pin 1 marked by a dot.

Pin/Terminal	Circuit Role	Design Meaning
1 (OE)	Output Enable	Active-high control: OE = 0 disables CLK+/CLK− outputs into high-impedance state; internal 17 kΩ pull-up ensures default enabled operation
2 (FS)	Frequency Select	Digital select line: FS = 0 selects first programmed frequency (f₀); FS = 1 selects second (f₁); internal 17 kΩ pull-up sets default to f₀
3 (GND)	Ground	Common reference for all signals and power; must be connected to low-impedance PCB ground plane to minimize jitter
4 (CLK+)	Differential Output+	LVDS true output; requires 100 Ω differential termination to achieve specified swing and symmetry
5 (CLK−)	Differential Output−	LVDS complementary output; paired with CLK+ for noise-rejecting differential clock delivery
6 (VDD)	Power Supply	3.3 V input (2.97–3.63 V); decoupling capacitor (≥100 nF) required adjacent to pin for DSPLL supply noise rejection

Key Features

Feature	Design Value
Dual-frequency programmability	Two distinct, factory-set frequencies selectable in-system via FS pin - eliminates need for multiple oscillators or rework in multi-clock designs
DSPLL® jitter performance	0.36 ps RMS phase jitter (125–500 MHz) - enables clean sampling clocks for high-speed SerDes and video interfaces
Fixed internal crystal	Single resonator architecture ensures <3 ppm aging/year and superior reliability vs. SAW-based oscillators
LVDS output compliance	Meets JEDEC JESD8-12 standards with 45–55% duty cycle and 0.5–0.9 VPP swing - interoperable with FPGA transceivers and ASIC clock inputs
Industrial temperature range	–40 to +85 °C operation with ±7 ppm stability - suitable for uncooled telecom line cards and broadcast equipment

Applications

SONET/SDH Line Cards	SD/HD Video Timing
Use Scenario: Generating synchronous 155.52 MHz (OC-3) and 622.08 MHz (OC-12) reference clocks for framer and mapper ICs in optical transport equipment. IC Role / Device Role / Timing Role: Primary low-jitter clock source providing dual-rate timing for SONET framers and clock data recovery (CDR) circuits. Use Value: DSPLL® supply noise rejection maintains sub-0.4 ps jitter under noisy backplane conditions, meeting GR-1244-CORE mask requirements.	Use Scenario: Driving pixel clocks for 1080p60 and 4K30 video processors in broadcast encoders and professional monitors. IC Role / Device Role / Timing Role: Dual-frequency XO supplying separate pixel clock (148.5 MHz) and audio sample rate (12.288 MHz) to SoC video subsystems. Use Value: ±7 ppm stability ensures frame sync integrity across multi-display genlock systems without external calibration.
FPGA Clock Generation	Networking Switch Fabric
Use Scenario: Providing configurable reference clocks to Xilinx Kintex or Intel Stratix FPGA banks requiring independent 100 MHz and 250 MHz inputs. IC Role / Device Role / Timing Role: Programmable dual-output clock generator replacing discrete crystal + PLL solutions on FPGA carrier boards. Use Value: Single 5×7 mm footprint reduces board area by >40% versus dual-XO implementations while maintaining pin-compatible layout.	Use Scenario: Delivering synchronized 125 MHz and 156.25 MHz clocks to Ethernet PHYs and switch fabric controllers in Layer 3 enterprise switches. IC Role / Device Role / Timing Role: Low-phase-noise timing source for IEEE 1588 PTP grandmaster synchronization and packet timestamping. Use Value: 0.34 ps RMS jitter (50 kHz–80 MHz) meets IEEE 802.3an (10GBASE-T) spectral purity requirements for deterministic latency.

SONET/SDH Line Cards

SD/HD Video Timing

Use Scenario: Generating synchronous 155.52 MHz (OC-3) and 622.08 MHz (OC-12) reference clocks for framer and mapper ICs in optical transport equipment.

IC Role / Device Role / Timing Role: Primary low-jitter clock source providing dual-rate timing for SONET framers and clock data recovery (CDR) circuits.

Use Value: DSPLL® supply noise rejection maintains sub-0.4 ps jitter under noisy backplane conditions, meeting GR-1244-CORE mask requirements.

Use Scenario: Driving pixel clocks for 1080p60 and 4K30 video processors in broadcast encoders and professional monitors.

IC Role / Device Role / Timing Role: Dual-frequency XO supplying separate pixel clock (148.5 MHz) and audio sample rate (12.288 MHz) to SoC video subsystems.

Use Value: ±7 ppm stability ensures frame sync integrity across multi-display genlock systems without external calibration.

FPGA Clock Generation

Networking Switch Fabric

Use Scenario: Providing configurable reference clocks to Xilinx Kintex or Intel Stratix FPGA banks requiring independent 100 MHz and 250 MHz inputs.

IC Role / Device Role / Timing Role: Programmable dual-output clock generator replacing discrete crystal + PLL solutions on FPGA carrier boards.

Use Value: Single 5×7 mm footprint reduces board area by >40% versus dual-XO implementations while maintaining pin-compatible layout.

Use Scenario: Delivering synchronized 125 MHz and 156.25 MHz clocks to Ethernet PHYs and switch fabric controllers in Layer 3 enterprise switches.

IC Role / Device Role / Timing Role: Low-phase-noise timing source for IEEE 1588 PTP grandmaster synchronization and packet timestamping.

Use Value: 0.34 ps RMS jitter (50 kHz–80 MHz) meets IEEE 802.3an (10GBASE-T) spectral purity requirements for deterministic latency.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency XO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si534/Si535 series (e.g., Si5342A-D-GM)	Higher integration: includes integrated jitter attenuator and multi-output fanout; wider frequency range (up to 2.2 GHz); consumes more power (140 mA typical)	Targeted at jitter-cleaning and distribution in high-end routers; not drop-in due to 8-pin QFN package and I²C configuration interface	Select when system requires sub-100 fs jitter cleaning or >2 output clocks; avoid if only dual-frequency generation and minimal BOM count are priorities
AK21E-100.0000T (Abracon)	Fixed dual-frequency (non-programmable); ±20 ppm stability; 3.3 V LVDS; same 5×7 mm 6-pin footprint and pinout	Limited to pre-defined frequency pairs (e.g., 100/125 MHz); no field-selectable switching; lower cost but no customization	Choose for cost-sensitive, high-volume applications where exact frequencies are known early and stability tolerance ≥±20 ppm is acceptable

Compared with Si534-series timing ICs, 533BC001080DG offers simpler integration and lower power for pure dual-frequency generation, while AK21E provides pin-compatible drop-in replacement only for fixed-frequency use cases - neither matches the 533BC001080DG's combination of ±7 ppm stability, factory-programmable dual frequencies, and DSPLL® noise immunity in identical packaging.

Availability

533BC001080DG is available at Aetrix Electronics and suitable for SONET/SDH line cards, SD/HD video processing systems, and FPGA-based prototyping platforms requiring stable component supply, guaranteed long-term continuity, and RoHS-compliant sourcing.

Supply support for 533BC001080DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The Si533 product line delivers highly stable, programmable crystal oscillators using DSPLL® synthesis for applications demanding low jitter, dual-frequency flexibility, and industrial temperature resilience - specifically targeting communications infrastructure and high-definition video systems.

FAQ

What output frequencies are supported by the 533BC001080DG?

The 533BC001080DG is factory-programmed with two specific frequencies selected from 10–945 MHz (or 970–1134 MHz / 1213–1417 MHz bands); CMOS output is limited to ≤160 MHz. The exact pair is encoded in the six-digit designator "001080" per Skyworks' part numbering convention and cannot be modified post-shipment.

Does the 533BC001080DG require external configuration or I²C programming?

No. The 533BC001080DG is fully factory-configured - its dual frequencies, output format (LVDS), supply voltage (3.3 V), temperature stability (±7 ppm), and OE/FS polarity are permanently programmed before shipment. No external interface, configuration pins beyond OE/FS, or firmware is needed for operation.

What is the function of the FS pin on the 533BC001080DG?

The FS (Frequency Select) pin on the 533BC001080DG is a digital input that toggles between the two factory-programmed output frequencies: FS = 0 selects the first frequency (f₀), and FS = 1 selects the second (f₁). It features an internal 17 kΩ pull-up resistor to VDD, defaulting to f₀ when left unconnected.

Can the 533BC001080DG operate with a 2.5 V or 1.8 V supply?

No. The "C" in the 533BC001080DG part number explicitly denotes the 3.3 V supply option. Devices with 2.5 V or 1.8 V supplies use different option codes (e.g., "E", "G", "J") and are distinct orderables - substituting a different supply voltage variant risks functional failure or damage.

Is the 533BC001080DG pin-compatible with other Si533 variants?

Yes. All Si533 devices - regardless of frequency, stability, output format, or supply voltage - share identical 5 × 7 mm 6-pin package dimensions, mechanical footprint, and pin assignments (OE, FS, GND, CLK+, CLK−, VDD), enabling direct PCB footprint reuse across the family.

533BC001080DG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si533

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 622.08MHz, 698.812MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVDS

Voltage - Supply:: 3.3V

Frequency Stability:: ±7ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 98mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

533BC001080DG FAQ

1.How can I place an order for 533BC001080DG through Aetrix?

Please submit a Request for Quotation (RFQ) for 533BC001080DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 533BC001080DG reliable?

The price and inventory of 533BC001080DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 533BC001080DG is usually 5 days.

3.What payment methods are accepted for 533BC001080DG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 533BC001080DG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 533BC001080DG?

533BC001080DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 533BC001080DG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 533BC001080DG?

For technical support, including 533BC001080DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 533BC001080DG requirements.

6.How does Aetrix verify that 533BC001080DG is sourced from the original manufacturer or authorized distributors?

All 533BC001080DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 533BC001080DG meets industry standards.

7.What is the process for return or replacement of 533BC001080DG?

All 533BC001080DG units undergo pre-shipment inspection (PSI). If there is an issue with 533BC001080DG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 533BC001080DG part is unused and in its original packaging.

Return procedure for 533BC001080DG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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