Skyworks Solutions Inc. 534AB000129DGR
- Part No.:
- 534AB000129DGR
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Pin Configurable/Selectable Oscillators
- Package:
- 8-SMD, No Lead
- Datasheet:
-
534AB000129DGR.pdf
- Description:
- XTAL OSC XO 3.3V 8SMD
- Quantity:
- Payment:

- Shipping:

Inventory:5,469
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Product details
Overview
534AB000129DGR from Skyworks Solutions is a factory-programmed quad-output crystal oscillator (XO) with DSPLL® frequency synthesis, delivering four selectable output frequencies between 10 MHz and 945 MHz (with select options up to 1.4 GHz), ±20 ppm temperature stability, LVDS output format, and 3.3 V supply. It serves as a low-jitter clock source in FPGA/ASIC timing, SD/HD video systems, and network infrastructure where multi-frequency flexibility and noise immunity are critical.
For engineers reviewing the 534AB000129DGR datasheet, 534AB000129DGR pinout, 534AB000129DGR application, or 534AB000129DGR equivalent, this device supports frequency selection via FS[1:0] pins, tristate control via OE, and operates across –40 °C to +85 °C with industry-standard 5 × 7 mm 8-pin package compatibility.
Technical Context
The 534AB000129DGR implements Skyworks' third-generation DSPLL® architecture, synthesizing four distinct output frequencies from a single internal fixed-frequency crystal-eliminating need for multiple crystals while ensuring high reliability and low aging (±3 ppm first-year drift). Its architecture provides superior supply noise rejection and enables stable low-jitter operation in electrically noisy communication environments.
Frequency selection is controlled by two logic inputs (FS[1], FS[0]), each with internal 17 kΩ pull-up resistors to VDD; outputs are differential LVDS with 100 Ω termination, mid-level at 1.20 V (typ), and 0.7 VPP (typ) swing. The device powers up in ≤10 ms and settles within 20 ms after FS[1:0] changes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Nominal Frequency Range | 10–945 MHz (any-rate); select frequencies up to 1400 MHz - supports flexible clock tree design without custom crystals |
| Output Format | LVDS - differential signaling with 100 Ω termination, enabling robust noise immunity and EMI reduction |
| Temperature Stability | ±20 ppm - ensures timing accuracy over full –40 °C to +85 °C industrial operating range |
| Phase Jitter (RMS) | 0.36 ps (12 kHz–20 MHz, 125–500 MHz output) - meets OC-48/OC-192 jitter compliance for telecom applications |
| Supply Voltage | 3.3 V (±10%) - compatible with standard digital logic rails and simplifies power delivery design |
| Package | 5 × 7 mm, 8-pin surface-mount - industry-standard footprint enabling drop-in replacement and PCB layout reuse |
| Aging (20-year life) | ±10 ppm - guarantees long-term frequency integrity in mission-critical embedded systems |
Pinout & Package
534AB000129DGR uses an industry-standard 5 × 7 mm, 8-pin surface-mount package with exposed pad (not electrically connected). Pin assignments follow Skyworks' Si534 LVDS/LVPECL/CML configuration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | NC | No connection - must be left unconnected; no internal function or electrical path |
| 2 | OE | Output enable - active-high control (1 = enabled, 0 = tristated); includes internal 17 kΩ pull-up to VDD |
| 3 | GND | Electrical and case ground - primary reference for all signals and power return path |
| 4 | CLK+ | Differential clock output positive - LVDS-compliant, requires 100 Ω termination to CLK– |
| 5 | CLK– | Differential clock output negative - complementary to CLK+, forms true differential pair |
| 6 | VDD | Power supply input - 3.3 V nominal; decoupling capacitor required near pin per layout guidelines |
| 7 | FS[1] | Frequency select MSB - selects one of four preprogrammed output frequencies; internal 17 kΩ pull-up |
| 8 | FS[0] | Frequency select LSB - used with FS[1] to define 00/01/10/11 states; internal 17 kΩ pull-up |
Key Features
| Feature | Design Value |
|---|---|
| Quad-frequency programmability | Four factory-configured output frequencies selected via dual-bit FS[1:0] interface - eliminates need for multiple oscillators or external MUX logic |
| DSPLL® jitter performance | 0.25–0.40 ps RMS phase jitter (12 kHz–20 MHz) for >500 MHz outputs - meets stringent SONET/SDH and high-speed serial link requirements |
| Fixed internal crystal | Single monolithic resonator ensures <±3 ppm first-year aging and exceptional long-term stability - reduces field failure risk vs. SAW-based alternatives |
| Supply noise rejection | Superior PSRR inherent to DSPLL architecture - maintains sub-picosecond jitter even under 50 mVpp supply ripple |
| RoHS-compliant packaging | Pb-free 5 × 7 mm 8-pin package with gold-over-nickel contact pads - compliant with IPC-7351 land pattern and JEDEC J-STD-020C reflow profiles |
Applications
| SONET/SDH Line Cards | Multi-Standard Video Equipment |
|---|---|
Use Scenario: Synchronous optical networking equipment requiring precise, switchable clock rates for OC-48/OC-192 data recovery and framing. IC Role / Device Role / Timing Role: Primary low-jitter reference oscillator providing four synchronized frequencies for SERDES, framer, and processor clocks. Use Value: Enables single-device support for multiple line rates (e.g., 622.08 MHz, 1244.16 MHz, 2488.32 MHz, 9953.28 MHz) without board-level redesign or additional components. |
Use Scenario: Broadcast-grade SD/HD/3G-SDI video encoders and routers needing clean, configurable pixel and reference clocks. IC Role / Device Role / Timing Role: Quad-output timing source generating parallel clocks for video processing, HDMI output, audio sampling, and system control logic. Use Value: Eliminates discrete crystal arrays and reduces BOM count while maintaining <1 ps period jitter for artifact-free video signal integrity. |
| FPGA-Based Test Instruments | Industrial Ethernet Switches |
Use Scenario: High-accuracy automated test equipment (ATE) using FPGA fabric for protocol emulation and signal generation. IC Role / Device Role / Timing Role: Configurable clock generator supplying independent clocks to FPGA I/O banks, ADC/DAC interfaces, and PCIe subsystems. Use Value: Allows dynamic clock rate switching during test sequences via FS[1:0], reducing test time and eliminating external clock switches or PLL reconfiguration delays. |
Use Scenario: Gigabit and 10GbE industrial switches operating in harsh ambient conditions (–40 °C to +85 °C). IC Role / Device Role / Timing Role: System timing hub providing PHY reference clocks, CPU core clocks, and management controller timing. Use Value: Delivers ±20 ppm stability over full temperature range and withstands thermal cycling per MIL-STD-883 - ensuring deterministic packet timing and PTP synchronization accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output XO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si534AB000129DG | Same silicon, identical specs, but shipped in cut tape instead of tape-and-reel (R suffix) | No functional difference; suitable for prototyping or low-volume assembly | Select when small-batch evaluation or manual placement is required |
| Si5351A-B-GM | Programmable I²C-controlled clock generator (not factory-configured); max 160 MHz output; CMOS-only; higher jitter (1.5 ps typical) | Requires host MCU and firmware; lacks DSPLL-based noise immunity and industrial temp rating | Choose only for cost-sensitive, non-critical, low-frequency applications where software configurability outweighs jitter and stability needs |
Compared with 534AB000129DGR, Si534AB000129DG offers identical electrical and thermal performance in alternate packaging, while Si5351A-B-GM trades factory precision and jitter performance for runtime programmability-making it unsuitable for telecom or broadcast timing where sub-0.5 ps jitter and ±20 ppm stability are mandatory.
Availability
534AB000129DGR is available at Aetrix Electronics and suitable for FPGA/ASIC clock generation, SD/HD video timing, and industrial Ethernet switching requiring stable component supply, guaranteed long-term availability, and RoHS-compliant sourcing.
Supply support for 534AB000129DGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for communications, automotive, and industrial markets.
The Si534 product line delivers highly stable, low-jitter, multi-output clock sources for high-speed digital systems-designed specifically to replace legacy crystal oscillators and simplify timing architecture in datacom, video, and test equipment.
FAQ
What output frequencies are programmed into the 534AB000129DGR?
The 534AB000129DGR is factory-programmed with four specific output frequencies determined by its six-digit frequency code "000129". Per Skyworks' ordering convention, this code maps to defined frequency pairs in the 10–945 MHz band. Exact values are specified in the device's configuration record and can be retrieved via Skyworks' ClockBuilder Pro tool using the full part number 534AB000129DGR.
Does the 534AB000129DGR support LVDS termination on-board?
No-the 534AB000129DGR does not include internal termination. It requires external 100 Ω differential termination between CLK+ and CLK– pins, as specified in Table 3 of the datasheet. This external resistor network ensures proper LVDS signal integrity, common-mode voltage control, and impedance matching for PCB traces.
Can the 534AB000129DGR operate at 2.5 V or 1.8 V supply?
No-the 534AB000129DGR is configured for 3.3 V operation, as indicated by the "A" in its second option code position (534AB000129DGR). Supply voltage is factory-set and not user-adjustable; applying 2.5 V or 1.8 V will result in improper functionality or failure to meet specifications.
Is the OE pin active-low or active-high on the 534AB000129DGR?
The OE pin on the 534AB000129DGR is active-high, as confirmed by the "A" in the first option code (534AB000129DGR), which denotes high-polarity output enable. When OE = 1 (≥0.75 × VDD), outputs are enabled; when OE = 0 (≤0.5 V), both CLK+ and CLK– enter high-impedance tristate mode.
What is the maximum allowable load capacitance for the 534AB000129DGR LVDS outputs?
The 534AB000129DGR LVDS outputs are designed for 100 Ω differential termination only-no capacitive loading beyond PCB trace parasitics is permitted. The datasheet specifies Rterm = 100 Ω (differential) and does not define or guarantee performance with added load capacitance; exceeding this violates the LVDS standard and degrades jitter and edge fidelity.
534AB000129DGR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si534
- Package/Case:
- 8-SMD, No Lead
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Base Resonator:
- Crystal
- Type:
- XO (Standard)
- Frequency - Output 1:
- 155.52MHz, 161.13281MHz, 167.33165MHz, 173.37075MHz
- Frequency - Output 2:
- -
- Frequency - Output 3:
- -
- Frequency - Output 4:
- -
- Function:
- Enable/Disable
- Output:
- LVPECL
- Voltage - Supply:
- 3.3V
- Frequency Stability:
- ±20ppm
- Operating Temperature:
- -40°C ~ 85°C
- Current - Supply (Max):
- 121mA
- Ratings:
- -
- Size / Dimension:
- 0.276" L x 0.197" W (7.00mm x 5.00mm)
- Height:
- 0.071" (1.80mm)
- Supplier Device Package:
- -
534AB000129DGR FAQ
1.How can I place an order for 534AB000129DGR through Aetrix?
Please submit a Request for Quotation (RFQ) for 534AB000129DGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 534AB000129DGR reliable?
The price and inventory of 534AB000129DGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 534AB000129DGR is usually 5 days.
3.What payment methods are accepted for 534AB000129DGR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 534AB000129DGR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 534AB000129DGR?
534AB000129DGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 534AB000129DGR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 534AB000129DGR?
For technical support, including 534AB000129DGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 534AB000129DGR requirements.
6.How does Aetrix verify that 534AB000129DGR is sourced from the original manufacturer or authorized distributors?
All 534AB000129DGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 534AB000129DGR meets industry standards.
7.What is the process for return or replacement of 534AB000129DGR?
All 534AB000129DGR units undergo pre-shipment inspection (PSI). If there is an issue with 534AB000129DGR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 534AB000129DGR part is unused and in its original packaging.
Return procedure for 534AB000129DGR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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