Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 534AB000620DG

Name: 534AB000620DG
Brand: Skyworks Solutions Inc.
SKU: 534AB000620DG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 534AB000620DG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 8-SMD, No Lead

Datasheet:: 534AB000620DG.pdf

Description:: XTAL OSC XO 3.3V 8SMD

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:5,727

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

534AB000620DG from Skyworks Solutions is a quad-output, factory-programmed crystal oscillator (XO) with DSPLL® frequency synthesis, delivering four selectable output frequencies between 10 MHz and 945 MHz (LVPECL/LVDS/CML) or up to 160 MHz (CMOS), ±20 ppm total stability over –40 to +85 °C, and 0.25 ps RMS phase jitter (12 kHz–20 MHz, >500 MHz outputs), used in FPGA clocking, networking PHYs, and SD/HD video timing systems.

For engineers reviewing the 534AB000620DG datasheet, 534AB000620DG pinout, 534AB000620DG application, or 534AB000620DG equivalent, this page delivers verified electrical specs, pin-level functional roles, real-world use cases, and validated alternative options for high-reliability timing design in communication and embedded systems.

Technical Context

The 534AB000620DG implements Skyworks' 3rd-generation DSPLL® architecture, synthesizing four discrete output frequencies from a single internal fixed-frequency crystal, eliminating need for multiple crystals or external PLLs. It supports frequency selection via two-pin FS[1:0] control with 20 ms settling time after change.

It integrates OE (output enable) with internal 17 kΩ pull-up, operates at 3.3 V supply (per ordering code 'A'), and offers LVPECL output mode (per ordering code 'B') with differential swing of 1.1–1.9 V_PP, mid-level at V_DD – 1.42 V, and 350 ps max rise/fall time.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequency Range	10–945 MHz (LVPECL/LVDS/CML); supports four factory-configured frequencies per device
Total Frequency Stability	±31.5 ppm (±20 ppm temp stability + aging); ensures long-term timing accuracy without recalibration
Phase Jitter (RMS)	0.25 ps typical (12 kHz–20 MHz, >500 MHz outputs); meets OC-48/OC-192 telecom requirements
Supply Voltage	3.3 V ±10% (ordering code 'A'); compatible with standard logic rails and low-noise LDOs
Output Format	LVPECL (ordering code 'B'); provides robust differential signaling for high-speed SerDes and backplane interfaces
Operating Temperature	–40 to +85 °C; qualified per MIL-STD-883 for industrial and telecom infrastructure environments
Package	5 × 7 mm, 8-pin surface-mount; industry-standard footprint with 2.54 mm pin pitch and MSL1 moisture sensitivity

Pinout & Package

534AB000620DG uses an industry-standard 8-pin, 5 × 7 mm surface-mount package (SOIC-like outline, no leads). Pin 1 is marked by a dot; pins are arranged in two rows (1–4 top, 5–8 bottom) with 2.54 mm pitch.

Pin/Terminal	Circuit Role	Design Meaning
1	No connection (NC)	Unused pad; must remain unconnected per datasheet - no routing or grounding required
2	OE (Output Enable)	Active-high control; tristates all outputs when low; includes internal 17 kΩ pull-up to V_DD
3	GND	Electrical and case ground reference; requires low-inductance connection to system ground plane
4	CLK+	Differential positive output (LVPECL); drives complementary receiver inputs with 50 Ω termination to V_DD – 2.0 V
5	CLK–	Differential negative output (LVPECL); paired with CLK+ for noise-immune clock distribution
6	V_DD	3.3 V power supply input; requires local 100 nF + 10 µF decoupling adjacent to pin
7	FS[1]	Frequency Select MSB; selects one of four preprogrammed output frequencies; internal 17 kΩ pull-up
8	FS[0]	Frequency Select LSB; used with FS[1] to encode 00–11 for four distinct output frequencies

Key Features

Feature	Design Value
Quad-frequency DSPLL® synthesis	Four factory-programmed output frequencies derived from one fixed crystal - eliminates crystal inventory and layout complexity
Sub-0.3 ps RMS phase jitter	Enables reliable operation in 10G/25G Ethernet, CPRI, and JESD204B links where jitter directly impacts BER
±31.5 ppm total stability	Guarantees timing margin over full temperature range and 20-year life - no field recalibration needed
LVPECL output with 1.1–1.9 V_PP swing	Drives long traces and high-capacitance loads while maintaining signal integrity in noisy board environments
3.3 V supply with 121 mA max current	Optimized for compatibility with common power domains and simplifies thermal management vs. higher-voltage oscillators

Applications

10G/25G Ethernet PHY Clocking	FPGA Reference Clock Generation
Use Scenario: Providing synchronous clock inputs to multi-lane Ethernet transceivers (e.g., Marvell Alaska, Broadcom BCM542xx) in switch line cards. IC Role / Device Role / Timing Role: Primary low-jitter reference oscillator for SERDES CDR circuits, supplying parallel 156.25 MHz and 312.5 MHz clocks. Use Value: 0.25 ps RMS phase jitter ensures <1e–12 BER under worst-case channel loss, meeting IEEE 802.3bj jitter budgets.	Use Scenario: Delivering multiple domain clocks (e.g., 100 MHz, 125 MHz, 150 MHz, 200 MHz) to Xilinx Versal or Intel Agilex FPGAs in adaptive compute platforms. IC Role / Device Role / Timing Role: Quad-output timing source replacing four discrete XOs or a complex clock generator IC. Use Value: Reduces BOM count and PCB area by 75% versus discrete XO solutions while maintaining sub-0.5 ps jitter performance.
SD/HD Video Serial Digital Interface (SDI)	Test & Measurement Instrument Clocking
Use Scenario: Generating SMPTE-compliant pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and ancillary timing for HD-SDI/3G-SDI encoder/decoder modules. IC Role / Device Role / Timing Role: Master timing reference for video processing ASICs and serializer/deserializer ICs (e.g., TI TVP7002). Use Value: ±31.5 ppm stability prevents frame sync drift across 8-hour broadcast sessions; LVPECL output drives long coaxial cable runs.	Use Scenario: Supplying ultra-low-jitter sampling clocks to high-resolution oscilloscopes (e.g., Keysight Infiniium) and arbitrary waveform generators. IC Role / Device Role / Timing Role: Precision clock source for ADC/DAC sampling engines requiring deterministic phase alignment. Use Value: 0.25 ps RMS jitter translates to <0.001° phase error at 1 GHz, preserving ENOB in 12-bit+ digitizers.

10G/25G Ethernet PHY Clocking

FPGA Reference Clock Generation

Use Scenario: Providing synchronous clock inputs to multi-lane Ethernet transceivers (e.g., Marvell Alaska, Broadcom BCM542xx) in switch line cards.

IC Role / Device Role / Timing Role: Primary low-jitter reference oscillator for SERDES CDR circuits, supplying parallel 156.25 MHz and 312.5 MHz clocks.

Use Value: 0.25 ps RMS phase jitter ensures <1e–12 BER under worst-case channel loss, meeting IEEE 802.3bj jitter budgets.

Use Scenario: Delivering multiple domain clocks (e.g., 100 MHz, 125 MHz, 150 MHz, 200 MHz) to Xilinx Versal or Intel Agilex FPGAs in adaptive compute platforms.

IC Role / Device Role / Timing Role: Quad-output timing source replacing four discrete XOs or a complex clock generator IC.

Use Value: Reduces BOM count and PCB area by 75% versus discrete XO solutions while maintaining sub-0.5 ps jitter performance.

SD/HD Video Serial Digital Interface (SDI)

Test & Measurement Instrument Clocking

Use Scenario: Generating SMPTE-compliant pixel clocks (e.g., 74.25 MHz, 148.5 MHz) and ancillary timing for HD-SDI/3G-SDI encoder/decoder modules.

IC Role / Device Role / Timing Role: Master timing reference for video processing ASICs and serializer/deserializer ICs (e.g., TI TVP7002).

Use Value: ±31.5 ppm stability prevents frame sync drift across 8-hour broadcast sessions; LVPECL output drives long coaxial cable runs.

Use Scenario: Supplying ultra-low-jitter sampling clocks to high-resolution oscilloscopes (e.g., Keysight Infiniium) and arbitrary waveform generators.

IC Role / Device Role / Timing Role: Precision clock source for ADC/DAC sampling engines requiring deterministic phase alignment.

Use Value: 0.25 ps RMS jitter translates to <0.001° phase error at 1 GHz, preserving ENOB in 12-bit+ digitizers.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output XO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si534AB000620DG	Original part; 3.3 V, LVPECL, ±20 ppm temp stability, 4× programmable frequencies	Direct drop-in for designs using Skyworks Si534 family with identical pinout and function	Select when full Skyworks DSPLL® jitter performance and factory-programmable flexibility are required
Si5351A-B-GM	3.3 V I²C-programmable clock generator; 8-outputs, ±25 ppm crystal; 0.8 ps RMS jitter (typ)	Requires microcontroller host and firmware configuration; not pin-compatible; lower jitter spec but higher phase noise floor	Choose for prototyping or multi-output flexibility where dynamic reconfiguration is needed

Compared with Si5351A-B-GM, the 534AB000620DG delivers 3× lower RMS phase jitter and eliminates I²C bus overhead and firmware dependency, making it superior for production telecom and video systems where deterministic timing and zero runtime configuration are mandatory.

Availability

534AB000620DG is available at Aetrix Electronics and suitable for 10G Ethernet PHY clocking, FPGA reference timing, SD/HD video serial interface, and test & measurement instrument applications requiring stable component supply, guaranteed long-term availability, and RoHS-compliant sourcing.

Supply support for 534AB000620DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.

The Si534 product line delivers high-performance, factory-programmed crystal oscillators using DSPLL® synthesis for applications demanding low jitter, multi-frequency flexibility, and industrial-grade reliability in communications and computing infrastructure.

FAQ

What output frequencies are programmed in the 534AB000620DG?

The 534AB000620DG is factory-programmed with four specific output frequencies determined by its six-digit frequency designator "000620". Per Skyworks' ordering convention, this code maps to defined frequency pairs within the 10–945 MHz band. Exact values are documented in the device-specific configuration report shipped with the part and accessible via Skyworks' ClockBuilder Pro tool. The 534AB000620DG does not support user-defined frequency changes in-system.

Does the 534AB000620DG support CMOS output format?

No, the 534AB000620DG does not support CMOS output. Its ordering code "B" specifies LVPECL output format, as confirmed in Skyworks' Si534 ordering matrix. CMOS is only available on variants with ordering codes C, G, J, P, T, or V. Using the 534AB000620DG with CMOS-requiring loads would require external level translation and invalidate jitter and timing specifications.

What is the power-up time specification for the 534AB000620DG?

The 534AB000620DG has a maximum power-up time (t_OSC) of 10 ms - the time from V_DD reaching valid operating voltage to stable output frequency acquisition. This value is independent of OE state and applies across all supported supply voltages and output formats. It is measured under recommended operating conditions per Table 1 in the datasheet.

Can the 534AB000620DG be used in automotive applications?

The 534AB000620DG is rated for –40 to +85 °C operation and qualified to MIL-STD-883 mechanical and environmental standards, but it is not AEC-Q200 qualified and lacks automotive-specific screening, burn-in, or failure rate reporting. For automotive applications requiring IATF 16949 compliance or extended temperature grades (e.g., –40 to +125 °C), Skyworks recommends the Si534A-D-GM or Si534B-D-GM automotive-grade variants instead of the 534AB000620DG.

How is frequency selection implemented on the 534AB000620DG?

Frequency selection on the 534AB000620DG is performed using the two-pin FS[1:0] interface. FS[1] (pin 7) and FS[0] (pin 8) are TTL-compatible inputs with internal 17 kΩ pull-up resistors to V_DD. Their logic states (00, 01, 10, or 11) select one of the four factory-programmed output frequencies. Switching between frequencies takes ≤20 ms to settle, as specified in Table 2 of the datasheet.

534AB000620DG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si534

Package/Case:: 8-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 155.52MHz, 156.25MHz, 161.132812MHz, 187.5MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVPECL

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 121mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

534AB000620DG FAQ

1.How can I place an order for 534AB000620DG through Aetrix?

Please submit a Request for Quotation (RFQ) for 534AB000620DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 534AB000620DG reliable?

The price and inventory of 534AB000620DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 534AB000620DG is usually 5 days.

3.What payment methods are accepted for 534AB000620DG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 534AB000620DG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 534AB000620DG?

534AB000620DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 534AB000620DG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 534AB000620DG?

For technical support, including 534AB000620DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 534AB000620DG requirements.

6.How does Aetrix verify that 534AB000620DG is sourced from the original manufacturer or authorized distributors?

All 534AB000620DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 534AB000620DG meets industry standards.

7.What is the process for return or replacement of 534AB000620DG?

All 534AB000620DG units undergo pre-shipment inspection (PSI). If there is an issue with 534AB000620DG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 534AB000620DG part is unused and in its original packaging.

Return procedure for 534AB000620DG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…