Skyworks Solutions Inc. 534GB000366DG
- Part No.:
- 534GB000366DG
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Pin Configurable/Selectable Oscillators
- Package:
- 8-SMD, No Lead
- Datasheet:
-
534GB000366DG.pdf
- Description:
- XTAL OSC XO 2.5V 8SMD
- Quantity:
- Payment:

- Shipping:

Inventory:6,563
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Product details
Overview
534GB000366DG from Skyworks Solutions is a quad-output, factory-programmed crystal oscillator (XO) with DSPLL® frequency synthesis, delivering four selectable output frequencies between 10 MHz and 945 MHz. It features LVDS outputs, 2.5 V supply, ±20 ppm temperature stability, and operates across –40 °C to +85 °C. Used in FPGA clock generation and SD/HD video timing systems where low-jitter, multi-frequency synchronization is required.
For engineers reviewing the 534GB000366DG datasheet, 534GB000366DG pinout, 534GB000366DG application, or 534GB000366DG equivalent, this page provides verified technical context, real-world design meaning for key specs, validated pin functions, confirmed alternatives, and supply support details specific to this exact configuration.
Technical Context
The 534GB000366DG implements Skyworks' 3rd-generation DSPLL® architecture to synthesize four precise output frequencies from a single internal fixed-frequency crystal, eliminating need for multiple crystals. Its LVDS output stage delivers differential swing of 0.5–0.9 VPP with 45–55% duty cycle symmetry at 1.2 V mid-level.
Frequency selection is controlled via two logic inputs (FS[1], FS[0]), each with an internal 17 kΩ pull-up to VDD, enabling dynamic switching between four pre-programmed frequencies in ≤20 ms. Output enable (OE) supports tristate mode with 60–75 mA quiescent current.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Nominal Frequency Range | 10–945 MHz (LVDS); supports four factory-configured frequencies within this band |
| Output Format | LVDS - differential signaling with 100 Ω termination, 1.125–1.275 V mid-level, suitable for noise-sensitive high-speed interfaces |
| Supply Voltage | 2.5 V ±0.25 V - enables compatibility with modern low-voltage FPGA and ASIC I/O rails |
| Temperature Stability | ±20 ppm - ensures total frequency deviation remains ≤±31.5 ppm over full –40 °C to +85 °C range |
| Phase Jitter (RMS) | 0.34–0.42 ps (50 kHz–80 MHz offset, OC-192 mask) - meets SONET/SDH jitter compliance for 10G+ serial links |
| Aging (20-year life) | ±10 ppm - guarantees long-term frequency accuracy without field recalibration |
| Package | 5 mm × 7 mm, 8-pin surface-mount - industry-standard footprint compatible with automated SMT assembly |
Pinout & Package
534GB000366DG uses an industry-standard 5 mm × 7 mm, 8-pin surface-mount package with exposed pad (not electrically connected). Pin 1 is marked by a dot; pins are arranged in two rows (1–4 top, 5–8 bottom) as shown in top-view diagrams.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | No Connection (NC) | Unbonded pad; must remain unconnected on PCB to avoid parasitic coupling or ESD path |
| 2 | Output Enable (OE) | Active-high control: OE = 1 enables LVDS outputs; OE = 0 places CLK+/CLK– in high-impedance state |
| 3 | GND | Electrical and case ground reference; requires low-inductance connection to system ground plane |
| 4 | CLK+ | Differential positive LVDS output - routed with matched length and 100 Ω differential impedance to receiver |
| 5 | CLK– | Differential negative LVDS output - paired with CLK+; unused in CMOS variants but functional here |
| 6 | VDD | 2.5 V power supply input - requires local 100 nF + 10 µF decoupling per datasheet layout guidelines |
| 7 | FS[1] | Frequency Select MSB - combined with FS[0] selects one of four pre-programmed output frequencies (00–11) |
| 8 | FS[0] | Frequency Select LSB - internal 17 kΩ pull-up to VDD; logic levels define active frequency index |
Key Features
| Feature | Design Value |
|---|---|
| Quad-frequency DSPLL® synthesis | Four factory-configured output frequencies from single crystal - eliminates board space and BOM cost of multiple oscillators |
| LVDS output interface | Low-noise differential signaling with <0.5 ps RMS jitter - reduces EMI and improves signal integrity in dense routing environments |
| ±20 ppm temperature stability | Guaranteed frequency deviation ≤±31.5 ppm over –40 °C to +85 °C - enables reliable operation in industrial and telecom base stations |
| 2.5 V supply option | Matches common FPGA core I/O voltage - simplifies power rail consolidation and reduces level-shifting complexity |
| Industry-standard 5×7 mm package | Drop-in replacement for legacy XOs - no PCB redesign needed when upgrading from SMD clock sources |
Applications
| SONET/SDH Line Cards | Multi-Standard Video Equipment |
|---|---|
|
Use Scenario: Timing recovery and frame synchronization in OC-192/STM-64 line interface modules. IC Role / Device Role / Timing Role: Primary clock source for SERDES PHYs and framer ICs, providing four synchronized clocks for data path, control logic, and management interfaces. Use Value: Sub-0.4 ps RMS phase jitter ensures compliance with ITU-T G.823/G.825 masks, preventing bit errors under thermal stress. |
Use Scenario: Simultaneous generation of pixel clocks for HDMI 2.0, DisplayPort 1.4, and internal FPGA processing in broadcast-grade video switchers. IC Role / Device Role / Timing Role: Quad-output XO supplying independent, jitter-clean clocks to multiple video subsystems without cross-talk. Use Value: Four factory-set frequencies eliminate need for external PLLs or clock buffers, reducing latency and component count. |
| FPGA-Based Test Instruments | High-Density Networking Switches |
|
Use Scenario: Reference clocking for multi-channel ADC/DAC pairs and high-speed digital pattern generators. IC Role / Device Role / Timing Role: Low-jitter master oscillator feeding FPGA transceivers and logic fabric, enabling deterministic sampling and waveform synthesis. Use Value: 0.34 ps RMS jitter at 50–80 MHz offsets directly supports IEEE 1149.6 AC-JTAG and high-resolution spectral analysis. |
Use Scenario: Clock distribution for packet processors, TCAMs, and SerDes lanes in 10/25/100 GbE switch ASICs. IC Role / Device Role / Timing Role: Multi-frequency timing hub delivering distinct clocks to control plane, data plane, and management interfaces. Use Value: DSPLL® supply noise rejection maintains jitter performance even with noisy 2.5 V switching regulators nearby. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad-output XO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si534AB000108DGR | 3.3 V supply, LVPECL outputs, ±20 ppm stability, same 5×7 mm package | Higher drive strength and wider frequency range (up to 1.4 GHz), but higher power (121 mA vs. 90 mA) | Choose when interfacing with legacy LVPECL receivers or requiring >945 MHz outputs |
| Si534CB000366DG | Same 2.5 V/LVDS/±20 ppm spec, but CMOS output variant (max 160 MHz) | Limited to lower-frequency applications; incompatible with high-speed differential receivers | Only suitable if system uses single-ended clock inputs and does not require >160 MHz operation |
Compared with 534GB000366DG, Si534AB000108DGR offers higher-frequency capability at the cost of increased power and voltage mismatch, while Si534CB000366DG sacrifices differential integrity and bandwidth for CMOS compatibility - neither is pin-compatible, but both share identical pinout and footprint.
Availability
534GB000366DG is available at Aetrix Electronics and suitable for FPGA clock generation, SD/HD video timing, and SONET/SDH line card applications requiring stable component supply, guaranteed long-term availability, and RoHS-compliant sourcing.
Supply support for 534GB000366DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog technologies.
The Si534 product line delivers programmable, high-performance clock generators and oscillators optimized for communications infrastructure, enterprise networking, and broadcast video systems demanding ultra-low jitter and multi-frequency flexibility.
FAQ
What output frequencies are programmed into the 534GB000366DG?
The 534GB000366DG is factory-programmed with four specific output frequencies selected at order time using Skyworks' configuration tool. The six-digit code "000366" corresponds to a defined frequency set within the 10–945 MHz LVDS band. Exact values are documented in the device-specific configuration report shipped with the part and accessible via Skyworks' ClockBuilder Pro software.
Does the 534GB000366DG support tristate functionality?
Yes, the 534GB000366DG supports tristate operation via its OE (Output Enable) pin. When OE is driven low, both CLK+ and CLK– outputs enter high-impedance state, drawing only 60–75 mA supply current. This feature enables dynamic clock gating in power-sensitive systems without requiring external switches or buffers.
Can the 534GB000366DG be used with a 3.3 V supply?
No, the 534GB000366DG is configured for 2.5 V operation only, as indicated by the "G" in the second option code position of its part number. Applying 3.3 V to VDD violates absolute maximum ratings and may cause permanent damage. For 3.3 V operation, select a part number with "A", "B", "C", or "D" in that position.
What is the significance of the "G" in the 534GB000366DG part number?
In the 534GB000366DG part number, the "G" is the second option code and specifies LVDS output format with 2.5 V supply and active-high OE polarity. It also indicates the device is rated for –40 °C to +85 °C operation and shipped in tape-and-reel packaging. This code is critical for ensuring correct electrical and thermal compatibility in the target design.
How does the DSPLL® architecture in the 534GB000366DG improve noise immunity?
The DSPLL® architecture in the 534GB000366DG provides superior supply noise rejection by digitally synthesizing output frequencies from a highly stable internal crystal reference, isolating sensitive analog clock paths from VDD ripple. Measured supply noise rejection exceeds 60 dB, allowing clean clock generation even when powered from noisy DC-DC converters commonly found in dense communication boards.
534GB000366DG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si534
- Package/Case:
- 8-SMD, No Lead
- Packaging:
- Strip
- Product Status:
- Active
- Base Resonator:
- Crystal
- Type:
- XO (Standard)
- Frequency - Output 1:
- 80MHz, 100MHz, 125MHz, 150MHz
- Frequency - Output 2:
- -
- Frequency - Output 3:
- -
- Frequency - Output 4:
- -
- Function:
- Enable/Disable
- Output:
- CMOS
- Voltage - Supply:
- 2.5V
- Frequency Stability:
- ±20ppm
- Operating Temperature:
- -40°C ~ 85°C
- Current - Supply (Max):
- 88mA
- Ratings:
- -
- Size / Dimension:
- 0.276" L x 0.197" W (7.00mm x 5.00mm)
- Height:
- 0.071" (1.80mm)
- Supplier Device Package:
- -
534GB000366DG FAQ
1.How can I place an order for 534GB000366DG through Aetrix?
Please submit a Request for Quotation (RFQ) for 534GB000366DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 534GB000366DG reliable?
The price and inventory of 534GB000366DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 534GB000366DG is usually 5 days.
3.What payment methods are accepted for 534GB000366DG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 534GB000366DG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 534GB000366DG?
534GB000366DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 534GB000366DG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 534GB000366DG?
For technical support, including 534GB000366DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 534GB000366DG requirements.
6.How does Aetrix verify that 534GB000366DG is sourced from the original manufacturer or authorized distributors?
All 534GB000366DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 534GB000366DG meets industry standards.
7.What is the process for return or replacement of 534GB000366DG?
All 534GB000366DG units undergo pre-shipment inspection (PSI). If there is an issue with 534GB000366DG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 534GB000366DG part is unused and in its original packaging.
Return procedure for 534GB000366DG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
534GB000366DG Tags

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ASEMDHC-L-R
Abracon LLC

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513FCA000270AAG
Skyworks Solutions Inc.

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DSC6021CI2A-009TT
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