Skyworks Solutions Inc. 535AC100M000DG

Overview

535AC100M000DG from Skyworks Solutions is an ultra-low-jitter, factory-programmed crystal oscillator (XO) delivering 100.000 MHz LVPECL output at 3.3 V supply with ±7 ppm temperature stability and ±3 ppm first-year aging. It uses DSPLL® synthesis for superior supply noise rejection and operates across –40 °C to +85 °C in data center and networking timing applications.

For engineers reviewing the 535AC100M000DG datasheet, 535AC100M000DG pinout, 535AC100M000DG application, or 535AC100M000DG equivalent, key selection criteria include phase jitter (0.25 ps RMS, 12 kHz–20 MHz), total frequency stability (±20 ppm), LVPECL drive capability, 5×7 mm package compatibility, and OE-controlled tristate functionality.

Technical Context

The 535AC100M000DG implements Skyworks' third-generation DSPLL® architecture, synthesizing its 100 MHz output from a fixed internal crystal reference-eliminating frequency-specific crystals while ensuring ±7 ppm temp stability and ±3 ppm aging. Its architecture enables high-power supply noise rejection (>60 dB typical) and fast 10 ms power-up time.

This Si535-series XO features LVPECL outputs with 1.1–1.9 V_PP differential swing, 50 Ω termination to VDD–2.0 V, and integrated 17 kΩ OE pull-up resistor. It supports active-high output enable on Pin 2 and operates in either enabled or high-impedance tristate mode with 60–75 mA quiescent current.

Key Specifications

Pinout & Package

535AC100M000DG is housed in an industry-standard, RoHS-compliant 6-pad, 5 × 7 mm surface-mount package (package outline per Figure 3, dimensions in Table 11). The Si535 variant places OE on Pin 2, distinguishing it from Si536's Pin 1 OE placement.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-jitter XO applications.

Compared with Si536AC100M000DG, the 535AC100M000DG offers identical timing performance but requires no PCB modification for existing Si535 footprints; versus AK2-100.000MHZ-E-T, it delivers lower jitter and LVPECL compatibility critical for high-speed SerDes.

Availability

535AC100M000DG is available at Aetrix Electronics and suitable for 10/40/100G data centers, 10G Ethernet switches/routers, and Fibre Channel storage systems requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.

Supply support for 535AC100M000DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications infrastructure, automotive, and industrial markets.

The Si535/536 product line delivers ultra-low-jitter, factory-programmed XOs using DSPLL® technology for high-speed serial data applications where timing integrity is mission-critical.

FAQ

What output format and supply voltage does the 535AC100M000DG use?

The 535AC100M000DG uses LVPECL output format and is specified for 3.3 V operation (2.97–3.63 V range). Its LVPECL outputs deliver 1.1–1.9 V_PP differential swing into 50 Ω loads terminated to VDD–2.0 V, making it compatible with high-speed FPGA and ASIC clock inputs without level translation. This configuration is confirmed in Tables 1 and 3 of the official Skyworks Si535/536 datasheet Rev. 1.3.

What is the frequency stability specification for the 535AC100M000DG over temperature?

The 535AC100M000DG has a temperature stability of ±7 ppm over the full operating range of –40 °C to +85 °C. This value is defined in Table 2 under "Temperature Stability" and corresponds to the 'C' option code in the part number convention. It contributes to the device's total stability of ±20 ppm, which also includes initial accuracy (±1.5 ppm) and aging (±3 ppm).

Does the 535AC100M000DG support output enable (OE), and how is it implemented?

Yes, the 535AC100M000DG supports hardware output enable on Pin 2 (OE), with active-high polarity. The OE pin includes an internal 17 kΩ pull-up resistor to VDD, so the output remains enabled upon power-up unless actively driven low. When OE = 0, both CLK+ and CLK− enter high-impedance tristate mode, drawing only 60–75 mA supply current. This behavior is documented in Table 9 (Si535 Pin Descriptions) and Section 2 of the datasheet.

What is the phase jitter performance of the 535AC100M000DG, and under what conditions is it measured?

The 535AC100M000DG achieves 0.25 ps RMS phase jitter measured over the 12 kHz to 20 MHz offset range, as specified in Table 4 of the datasheet. This value applies to all supported frequencies including 100 MHz and reflects the device's DSPLL® architecture performance under typical operating conditions (VDD = 3.3 V, TA = 25 °C). It meets OC-192 and 100G Ethernet jitter requirements.

Is the 535AC100M000DG RoHS-compliant and qualified for industrial temperature operation?

Yes, the 535AC100M000DG is Pb-free and RoHS-compliant (indicated by final 'G' and '+' mark per Table 13), and is fully qualified for industrial temperature operation from –40 °C to +85 °C. Its qualification includes MIL-STD-883 mechanical shock/vibration testing, J-STD-020C MSL1 moisture sensitivity rating, and JEDEC-compliant soldering profiles up to 260 °C peak temperature.