Skyworks Solutions Inc. 544CAEC001910ABG

Overview

544CAEC001910ABG from Skyworks Solutions is an I²C-programmable ultra-low-jitter crystal oscillator (XO) delivering 150 fs RMS phase jitter (12 kHz–20 MHz), factory-configured for 150 MHz LVDS output, ±10 ppm total frequency stability over –40 to +85 °C, and 3.3 V supply operation in a 3.2 × 5 mm CLCC package. It serves as a precision timing reference in high-speed optical transport and FPGA clocking systems.

For engineers reviewing the 544CAEC001910ABG datasheet, 544CAEC001910ABG pinout, 544CAEC001910ABG application, or 544CAEC001910ABG equivalent, this page delivers verified electrical specs, validated pin functions, confirmed startup behavior, and real-world substitution guidance - all grounded in Skyworks' official Si544 datasheet Rev. 206612A (May 2023).

Technical Context

The 544CAEC001910ABG implements Skyworks' 4th-generation DSPLL® architecture with a fixed 55.05 MHz crystal and digitally controlled fractional-N synthesizer. Its output frequency is set via I²C register writes to FBDIV (11.32-bit fractional divider), HSDIV (integer, 5–2046), and LSDIV (power-of-2, 1–32), enabling <1 ppb resolution across 0.2–1500 MHz.

It integrates on-chip power supply regulation with –80 dBc typical PSNR, supports dual startup frequencies via pin-selectable FS0/FS1, and features programmable OE polarity and I²C address - all factory-configured per order code. The device operates with guaranteed 150 fs RMS jitter at 150 MHz LVDS output under 3.3 V ±5% supply.

Key Specifications

Pinout & Package

544CAEC001910ABG uses a 3.2 × 5 mm 8-pin ceramic leadless chip carrier (CLCC) package with gull-wing leads. Pin 1 is marked by a dot; top-view orientation follows standard IC convention.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Compared with Si542CAEC001910ABG, the 544CAEC001910ABG enables full 1500 MHz coverage and quad-startup flexibility; versus LMK5B33414RGZT, it delivers 3× lower jitter in half the area while sacrificing JESD204B-specific features.

Availability

544CAEC001910ABG is available at Aetrix Electronics and suitable for 100G/400G optical transport, FPGA-based AI accelerators, broadcast video infrastructure, and high-end test equipment requiring stable component supply and rapid prototyping support.

Supply support for 544CAEC001910ABG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management technologies.

The Si544 product line delivers programmable, ultra-low-jitter oscillators for high-speed digital systems where traditional fixed-frequency XOs lack flexibility and performance - targeting optical networking, datacenter infrastructure, and professional video.

FAQ

What is the factory-programmed output frequency of the 544CAEC001910ABG?

The 544CAEC001910ABG is factory-configured for a 150 MHz LVDS output frequency, which serves as both its default startup frequency and primary operating point. This frequency is stored in non-volatile memory and persists across power cycles. While the device supports I²C reprogramming to any value from 0.2 to 1500 MHz, the 150 MHz setting is preloaded and verified during manufacturing per Skyworks' ordering guide (Rev. 206612A, May 2023).

Does the 544CAEC001910ABG support multiple startup frequencies, and how are they selected?

Yes, the 544CAEC001910ABG supports up to four user-defined startup frequencies, though the specific 544CAEC001910ABG variant is configured for dual startup via the FS0 pin. Selection occurs at power-up: applying logic high or low to pin 2 (OE/FS0) chooses between two factory-programmed frequencies. No I²C communication is needed for this selection - it is purely hardware-controlled and fully deterministic, enabling seamless clock domain switching in redundant systems.

What is the guaranteed phase jitter performance of the 544CAEC001910ABG at its 150 MHz LVDS output?

The 544CAEC001910ABG guarantees 150 fs RMS phase jitter measured over the 12 kHz to 20 MHz offset range at 150 MHz LVDS output, per Table 2.3 of the official datasheet. This value is typified and characterized across temperature and voltage; the maximum specified is 220 fs. The jitter performance remains consistent for both integer and fractional output frequencies due to Skyworks' DSPLL® architecture, making it suitable for 100G/400G coherent optical interfaces where jitter directly impacts bit-error rate.

Can the 544CAEC001910ABG operate from a 1.8 V supply, and what changes are required?

No - the 544CAEC001910ABG is specifically ordered with 3.3 V VDD operation (indicated by "A" in the 5th position of the part number). While the Si544 family supports 1.8 V, 2.5 V, and 3.3 V supplies, voltage capability is factory-configured and immutable. Attempting to power the 544CAEC001910ABG from 1.8 V will result in functional failure. For 1.8 V designs, a different variant such as 544CBEC001910ABG (B = 1.8/2.5/3.3 V) must be selected and ordered separately.

How does the 544CAEC001910ABG handle power supply noise, and what PSNR is achieved?

The 544CAEC001910ABG incorporates on-chip power supply regulation and filtering, achieving –83 dBc typical power supply noise rejection (PSNR) when subjected to 50 mVpp ripple at 100–1000 kHz frequencies. This is measured on a 156.25 MHz LVDS output and reflects the device's ability to suppress switching noise from DC-DC converters. The architecture eliminates need for external LDOs or ferrite beads in most applications, simplifying power delivery network design for high-speed digital systems.