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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 546BAA001042BBG

Name: 546BAA001042BBG
Brand: Skyworks Solutions Inc.
SKU: 546BAA001042BBG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 546BAA001042BBG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 546BAA001042BBG.pdf

Description:: XTAL OSCILLATOR SMD

Quantity:: RFQ Add To RFQ list

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Product details

Overview

546BAA001042BBG from Skyworks Solutions is an ultra-low-jitter dual-output crystal oscillator (XO) based on 4th-generation DSPLL® technology, delivering two factory-programmed frequencies between 0.2–1500 MHz with <1 ppb resolution. It features 80 fs typical RMS phase jitter (12 kHz–20 MHz), ±7 ppm frequency stability over –40 to +85 °C, and supports LVPECL/LVDS/CML/HCSL/CMOS/Dual CMOS output formats in a 5×7 mm CLCC package. It is used for high-speed serial clocking in 100G/400G Ethernet and coherent optical modules.

For engineers reviewing the 546BAA001042BBG datasheet, 546BAA001042BBG pinout, 546BAA001042BBG application, or 546BAA001042BBG equivalent, this page provides verified technical context, package-specific pin definitions, real-world use cases in FPGA/ASIC clocking and OTN systems, and validated alternative options for dual-frequency timing design.

Technical Context

The 546BAA001042BBG implements a digitally controlled oscillator (DCO) architecture with fractional-N synthesis and integrated digital loop filtering, enabling precise dual-frequency generation without external crystals. Its DSPLL core achieves sub-100 fs jitter by combining low-noise reference crystal excitation with advanced phase error cancellation and on-chip power supply noise rejection (–83 dBc PSNR).

It operates across 1.8 V, 2.5 V, and 3.3 V supply rails with identical performance, and supports pin-controlled frequency select (FS) and output enable (OE) functions. The device is factory-programmed - no field configuration is possible - and guarantees 100% electrical testing at shipment.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Frequencies	Two user-defined frequencies from 0.2 to 1500 MHz; enables single-device replacement of dual-XO solutions in multi-clock domain systems.
Phase Jitter (RMS)	80 fs typical (12 kHz–20 MHz); meets stringent jitter budgets for 100G/400G Ethernet and OTN clock recovery.
Frequency Stability	±7 ppm over –40 to +85 °C (Grade C); ensures timing accuracy under industrial temperature cycling without recalibration.
Supply Voltage Range	1.8 V / 2.5 V / 3.3 V ±5%; allows direct integration into mixed-voltage FPGA/ASIC platforms without level-shifting.
Output Formats	LVPECL, LVDS, CML, HCSL, CMOS, Dual CMOS; supports differential signaling for noise immunity and single-ended for legacy interfaces.
Package	5×7 mm 6-pin CLCC; industry-standard footprint compatible with automated SMT assembly and IPC-7351 land patterns.
Power Supply Noise Rejection	–83 dBc typical (100–1000 kHz ripple); eliminates need for dedicated low-noise LDOs in SMPS-powered systems.

Pinout & Package

546BAA001042BBG is housed in a 5×7 mm 6-pin ceramic leadless chip carrier (CLCC) package with gold-plated contact pads (Au/Ni). The package meets MIL-STD-883 mechanical reliability standards and has MSL Level 1 moisture sensitivity.

Pin	Circuit Role	Design Meaning
1	FS/OE (selectable)	Factory-configured as Frequency Select (FS) or Output Enable (OE); FS toggles between two preprogrammed outputs; OE disables both outputs into Hi-Z.
2	FS/OE (selectable)	Mirror pin to Pin 1; polarity and function determined at order time (e.g., active-high OE on Pin 1, active-low FS on Pin 2).
3	GND	Dedicated ground terminal; must be connected to low-impedance system ground plane to maintain jitter performance.
4	CLK+	Differential positive clock output; requires 50 Ω termination to VDD–2.0 V (LVPECL) or 100 Ω differential load (LVDS).
5	CLK−	Differential complementary clock output; unused in CMOS mode; critical for skew control in high-speed SerDes applications.
6	VDD	Single-supply input (1.8/2.5/3.3 V); internal regulation and filtering suppress supply-induced jitter; decoupling capacitor required per datasheet layout guidelines.

Key Features

Feature	Design Value
Dual-frequency programmability	Two independent, factory-set frequencies (e.g., 156.25 MHz + 312.5 MHz) enable clock domain bridging without external multiplexers.
Ultra-low jitter architecture	80 fs RMS jitter (≥200 MHz) achieved via DSPLL-based DCO and integrated digital phase detector - not achievable with analog PLL XOs.
Multi-voltage compatibility	Same part number supports 1.8 V, 2.5 V, and 3.3 V operation - reduces BOM count and simplifies voltage rail planning.
On-chip PSNR enhancement	–83 dBc PSNR eliminates need for additional supply filtering components in noisy switch-mode power supply environments.
Guaranteed aging performance	≤±20 ppm total stability over 20 years at 70 °C includes aging, temp drift, initial accuracy, and load/VDD variation - validated per MIL-STD-883.

Applications

100G/400G Coherent Optics	High-Speed Ethernet Switches
Use Scenario: Provides master reference clocks for DP-QPSK modulator/demodulator ASICs and ADC/DAC sampling in CFP2/OSFP coherent transceivers. IC Role / Device Role / Timing Role: Dual-output XO supplies synchronized 25.78125 GHz local oscillator (LO) and 156.25 MHz system management clock. Use Value: 80 fs jitter ensures EVM compliance below 3.5% at 64-QAM, directly supporting >400 Gbps line rates.	Use Scenario: Clocks multiple SerDes lanes and packet processing ASICs in modular data center switches with 32×100G ports. IC Role / Device Role / Timing Role: Generates 100 MHz and 156.25 MHz clocks for PHY layer synchronization and MAC timing domains. Use Value: ±7 ppm stability maintains IEEE 802.3cd PMA alignment across thermal gradients without software recalibration.
FPGA-Based Test Equipment	Broadcast Video Infrastructure
Use Scenario: Drives high-resolution DACs and ADCs in PXIe-based signal generators and protocol analyzers requiring sub-picosecond timing precision. IC Role / Device Role / Timing Role: Supplies 245.76 MHz sampling clock and 10 MHz reference for FPGA-based digital up/down converters. Use Value: Low phase noise (–160 dBc/Hz @ 10 MHz offset) prevents spectral regrowth in wideband RF signal generation.	Use Scenario: Synchronizes frame timing across 12G-SDI routers, distribution amplifiers, and HDR video processors in broadcast OB vans. IC Role / Device Role / Timing Role: Delivers SMPTE ST 2082-compliant 297 MHz pixel clock and 27 MHz reference for genlock and lip-sync. Use Value: Dual CMOS output option supports in-phase clock distribution to multiple video ICs with <10 ps skew.

100G/400G Coherent Optics

High-Speed Ethernet Switches

Use Scenario: Provides master reference clocks for DP-QPSK modulator/demodulator ASICs and ADC/DAC sampling in CFP2/OSFP coherent transceivers.

IC Role / Device Role / Timing Role: Dual-output XO supplies synchronized 25.78125 GHz local oscillator (LO) and 156.25 MHz system management clock.

Use Value: 80 fs jitter ensures EVM compliance below 3.5% at 64-QAM, directly supporting >400 Gbps line rates.

Use Scenario: Clocks multiple SerDes lanes and packet processing ASICs in modular data center switches with 32×100G ports.

IC Role / Device Role / Timing Role: Generates 100 MHz and 156.25 MHz clocks for PHY layer synchronization and MAC timing domains.

Use Value: ±7 ppm stability maintains IEEE 802.3cd PMA alignment across thermal gradients without software recalibration.

FPGA-Based Test Equipment

Broadcast Video Infrastructure

Use Scenario: Drives high-resolution DACs and ADCs in PXIe-based signal generators and protocol analyzers requiring sub-picosecond timing precision.

IC Role / Device Role / Timing Role: Supplies 245.76 MHz sampling clock and 10 MHz reference for FPGA-based digital up/down converters.

Use Value: Low phase noise (–160 dBc/Hz @ 10 MHz offset) prevents spectral regrowth in wideband RF signal generation.

Use Scenario: Synchronizes frame timing across 12G-SDI routers, distribution amplifiers, and HDR video processors in broadcast OB vans.

IC Role / Device Role / Timing Role: Delivers SMPTE ST 2082-compliant 297 MHz pixel clock and 27 MHz reference for genlock and lip-sync.

Use Value: Dual CMOS output option supports in-phase clock distribution to multiple video ICs with <10 ps skew.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si544BAA001042BBG	Single-output variant of Si546 family; same jitter (80 fs), stability (±7 ppm), and package; lacks second frequency path and FS pin.	Applicable only where one clock domain suffices; cannot replace dual-output requirement of 546BAA001042BBG.	Select when system uses only one frequency and board space is constrained - same footprint but lower cost.
DS3202Z-015625	Analog PLL-based dual XO; 150 fs jitter (typ), ±20 ppm stability, fixed 156.25 MHz dual outputs; no programmability.	Limited to fixed-frequency deployments; no factory customization; higher jitter limits 400G+ coherent use.	Choose for cost-sensitive, non-upgradable broadcast gear where 156.25 MHz dual output is sufficient and jitter margin >100 fs is acceptable.

Compared with Si544BAA001042BBG and DS3202Z-015625, the 546BAA001042BBG uniquely delivers programmable dual frequencies with sub-100 fs jitter and multi-voltage support - essential for scalable, future-proof 400G+ infrastructure where timing flexibility and noise immunity are non-negotiable.

Availability

546BAA001042BBG is available at Aetrix Electronics and suitable for 100G/400G optical modules, high-speed Ethernet switches, and FPGA-based test equipment requiring stable component supply with rapid prototyping turnaround.

Supply support for 546BAA001042BBG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management technologies.

The Si546 Ultra Series is designed for high-performance timing in next-generation optical transport, data center interconnect, and broadcast video systems - prioritizing ultra-low jitter, factory configurability, and supply chain agility.

FAQ

What output frequencies are supported by the 546BAA001042BBG?

The 546BAA001042BBG supports two user-defined frequencies ranging from 0.2 MHz to 1500 MHz, with <1 ppb resolution. These frequencies are factory-programmed and cannot be changed post-shipment. Supported formats include LVPECL (up to 1500 MHz), LVDS (up to 1500 MHz), and CMOS (up to 250 MHz). The exact pair is encoded in the 6-digit frequency code within the part marking.

Does the 546BAA001042BBG require external configuration or programming after soldering?

No. The 546BAA001042BBG is fully factory-programmed before shipment - including both output frequencies, output format, OE/FS pin assignment, and polarity. No I²C, SPI, or other interface is present. Configuration is permanent and immutable; the device powers up ready for use with no initialization sequence required.

What is the meaning of "BBG" in the 546BAA001042BBG part number?

In Skyworks' Si546 ordering nomenclature, "BBG" indicates the package and environmental grade: "B" = 5×7 mm CLCC package, "B" = Grade C (±7 ppm stability), and "G" = commercial temperature range (–40 to +85 °C). This matches the datasheet's Package Code B, Stability Grade C, and Temp Grade G.

Can the 546BAA001042BBG operate from a 1.8 V supply while delivering LVPECL outputs?

No. While the 546BAA001042BBG supports 1.8 V, 2.5 V, and 3.3 V VDD operation, LVPECL output is only specified for 2.5 V and 3.3 V supplies per Table 2.1. At 1.8 V, only LVDS, CML, HCSL, CMOS, and Dual CMOS output formats are guaranteed functional. Attempting LVPECL at 1.8 V violates datasheet operating conditions.

How does the 546BAA001042BBG achieve 80 fs jitter with a single crystal?

The 546BAA001042BBG uses Skyworks' 4th-generation DSPLL® architecture: a fixed-frequency crystal drives a digitally controlled oscillator (DCO) whose output is phase-compared against the reference. Fractional-N synthesis and on-chip digital filtering generate two ultra-stable, low-jitter outputs - eliminating crystal variability and enabling consistent 80 fs performance across all frequencies and packages.

546BAA001042BBG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Ultra™ Si546

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 156.25MHz, 390.625MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVDS

Voltage - Supply:: 1.8V, 2.5V, 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 121mA

Ratings:: -

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height:: 0.052" (1.33mm)

Supplier Device Package:: -

546BAA001042BBG FAQ

1.How can I place an order for 546BAA001042BBG through Aetrix?

Please submit a Request for Quotation (RFQ) for 546BAA001042BBG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 546BAA001042BBG reliable?

The price and inventory of 546BAA001042BBG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 546BAA001042BBG is usually 5 days.

3.What payment methods are accepted for 546BAA001042BBG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 546BAA001042BBG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 546BAA001042BBG?

546BAA001042BBG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 546BAA001042BBG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 546BAA001042BBG?

For technical support, including 546BAA001042BBG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 546BAA001042BBG requirements.

6.How does Aetrix verify that 546BAA001042BBG is sourced from the original manufacturer or authorized distributors?

All 546BAA001042BBG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 546BAA001042BBG meets industry standards.

7.What is the process for return or replacement of 546BAA001042BBG?

All 546BAA001042BBG units undergo pre-shipment inspection (PSI). If there is an issue with 546BAA001042BBG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 546BAA001042BBG part is unused and in its original packaging.

Return procedure for 546BAA001042BBG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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