Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 546CAA001038BBG

Name: 546CAA001038BBG
Brand: Skyworks Solutions Inc.
SKU: 546CAA001038BBG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 546CAA001038BBG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 546CAA001038BBG.pdf

Description:: XTAL OSCILLATOR SMD

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,152

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

546CAA001038BBG from Skyworks Solutions is an ultra-low-jitter dual-output crystal oscillator (XO) based on 4th-generation DSPLL® technology, delivering two factory-programmed frequencies between 0.2–1500 MHz with <1 ppb resolution. It features 80 fs typical RMS phase jitter (12 kHz–20 MHz), ±7 ppm frequency stability over –40 to +85 °C, and supports LVPECL/LVDS/CML/HCSL/CMOS/Dual CMOS output formats. It is deployed in high-speed optical transport and Ethernet timing systems requiring deterministic clocking.

For engineers reviewing the 546CAA001038BBG datasheet, 546CAA001038BBG pinout, 546CAA001038BBG application, or 546CAA001038BBG equivalent, this page provides verified package mapping (5×7 mm CLCC), confirmed dual-frequency configuration capability, validated supply noise rejection (–80 dBc typ), and real-world FPGA/ASIC clocking and coherent optics use cases - all directly traceable to Skyworks' official Si546 datasheet revision 206614A (May 2023).

Technical Context

The 546CAA001038BBG implements a digitally controlled oscillator (DCO) architecture with fractional-N divider and digital phase detector, enabling precise synthesis of both integer and fractional frequencies without crystal swapping. Its on-chip power supply regulation delivers –80 dBc typical PSNR, decoupling clock integrity from noisy switched-mode supplies.

Factory-programmed configuration includes dual-frequency selection (FS pin-controlled), OE polarity, and output format - all set at shipment. The device uses a single fixed-frequency crystal combined with DSPLL-based frequency translation, guaranteeing 100% electrical testing and eliminating custom crystal lead times.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Frequencies	Two user-selectable frequencies from 0.2 to 1500 MHz; enables single-device replacement of dual-XO solutions in multi-clock domain systems.
Phase Jitter (RMS)	80 fs typical (12 kHz–20 MHz, ≥200 MHz output); meets stringent BER requirements for 400G OTN and 25G+ SerDes interfaces.
Frequency Stability	±7 ppm over –40 to +85 °C (Grade C); ensures timing margin retention across industrial temperature operation without recalibration.
Supply Voltage	1.8 V / 2.5 V / 3.3 V selectable via same part number; simplifies BOM consolidation across mixed-voltage board designs.
Output Formats	LVPECL, LVDS, CML, HCSL, CMOS, Dual CMOS; supports direct interface to FPGAs, ASICs, SERDES PHYs, and SDI video processors.
Package	5×7 mm 6-pin CLCC; industry-standard footprint compatible with automated SMT placement and IPC-7351-compliant land pattern (C1=4.20 mm, E=2.54 mm).
Power Supply Noise Rejection	–80 dBc typical PSNR; maintains low jitter in systems powered by DC/DC converters without additional LDO filtering.

Pinout & Package

546CAA001038BBG is housed in a 5×7 mm 6-pin ceramic leadless chip carrier (CLCC) package with gold-plated Ni/Au contact pads (0.3–1.0 µm Au / 1.27–8.89 µm Ni), MSL Level 1, and JEDEC J-STD-020-compliant reflow profile.

Pin/Terminal	Circuit Role	Design Meaning
1	FS/OE (selectable)	Factory-configured as Frequency Select (FS) or Output Enable (OE); FS toggles between two programmed frequencies; OE disables outputs to Hi-Z state.
2	FS/OE (selectable)	Mirror terminal for FS/OE function; polarity (active-high/low) and pin assignment defined at order time per Skyworks ordering guide.
3	GND	Dedicated ground reference for internal PLL and output drivers; requires low-inductance connection to system ground plane.
4	CLK+	Differential positive clock output; valid for LVPECL, LVDS, CML, HCSL, and Dual CMOS modes; not used in single-ended CMOS.
5	CLK−	Differential complementary clock output; required for all differential formats; internally terminated; unused in CMOS mode.
6	VDD	Single-supply input (1.8/2.5/3.3 V ±5%); incorporates on-chip regulation and filtering to suppress supply-induced jitter.

Key Features

Feature	Design Value
Dual-frequency programmability	Two independent frequencies (e.g., 156.25 MHz + 312.5 MHz) factory-set with <1 ppb resolution; eliminates need for multiple oscillators or external muxing.
Ultra-low phase jitter	80 fs RMS (12 kHz–20 MHz) at ≥200 MHz; enables clean sampling clocks for high-speed ADCs, DACs, and coherent optical modulators.
Multi-voltage supply support	Operates identically across 1.8 V, 2.5 V, and 3.3 V rails using same part number; reduces inventory complexity and layout variants.
On-chip supply noise rejection	–80 dBc typical PSNR; allows direct connection to noisy DC/DC outputs without external LDOs or ferrite beads in space-constrained designs.
Configurable output enable	OE pin (pin 1 or 2) supports active-high/low polarity; enables dynamic clock gating for power management in FPGA-based accelerators.

Applications

100G/400G Coherent Optics	High-Speed Ethernet Switching
Use Scenario: Timing recovery and laser modulation in DP-QPSK/16-QAM coherent transceivers operating at 200G/400G line rates. IC Role / Device Role / Timing Role: Primary reference clock source for ADC/DAC sampling, DSP clocking, and FEC engine synchronization. Use Value: 80 fs jitter ensures <1e-15 BER under PAM4 signaling; dual-frequency output supports separate TX/RX clock domains without skew.	Use Scenario: Clock distribution in 25G/100G Ethernet switch ASICs and NICs with multi-lane SerDes arrays. IC Role / Device Role / Timing Role: Low-jitter master clock feeding multiple SerDes PLLs and packet buffer controllers. Use Value: ±7 ppm stability guarantees link lock across temperature; LVDS outputs drive 100 Ω differential traces with <350 ps edge rates.
Broadcast Video (12G-SDI/24G-SDI)	FPGA-Based Compute Acceleration
Use Scenario: Genlock and frame-synchronous timing in UHD/8K broadcast cameras and production switchers. IC Role / Device Role / Timing Role: Reference oscillator for SMPTE ST 2082-1 compliant 12G-SDI serializers and reclockers. Use Value: Dual CMOS output option provides in-phase 270 MHz and 540 MHz clocks for pixel clock and DDR memory interface timing.	Use Scenario: Clock provisioning for AI inference accelerators using Xilinx Versal or Intel Agilex FPGAs with hardened PCIe/DDR subsystems. IC Role / Device Role / Timing Role: Configurable dual-frequency source for FPGA fabric clock and transceiver reference clock domains. Use Value: FS pin allows runtime switching between 300 MHz (compute) and 250 MHz (PCIe Gen4) frequencies without firmware reload.

100G/400G Coherent Optics

High-Speed Ethernet Switching

Use Scenario: Timing recovery and laser modulation in DP-QPSK/16-QAM coherent transceivers operating at 200G/400G line rates.

IC Role / Device Role / Timing Role: Primary reference clock source for ADC/DAC sampling, DSP clocking, and FEC engine synchronization.

Use Value: 80 fs jitter ensures <1e-15 BER under PAM4 signaling; dual-frequency output supports separate TX/RX clock domains without skew.

Use Scenario: Clock distribution in 25G/100G Ethernet switch ASICs and NICs with multi-lane SerDes arrays.

IC Role / Device Role / Timing Role: Low-jitter master clock feeding multiple SerDes PLLs and packet buffer controllers.

Use Value: ±7 ppm stability guarantees link lock across temperature; LVDS outputs drive 100 Ω differential traces with <350 ps edge rates.

Broadcast Video (12G-SDI/24G-SDI)

FPGA-Based Compute Acceleration

Use Scenario: Genlock and frame-synchronous timing in UHD/8K broadcast cameras and production switchers.

IC Role / Device Role / Timing Role: Reference oscillator for SMPTE ST 2082-1 compliant 12G-SDI serializers and reclockers.

Use Value: Dual CMOS output option provides in-phase 270 MHz and 540 MHz clocks for pixel clock and DDR memory interface timing.

Use Scenario: Clock provisioning for AI inference accelerators using Xilinx Versal or Intel Agilex FPGAs with hardened PCIe/DDR subsystems.

IC Role / Device Role / Timing Role: Configurable dual-frequency source for FPGA fabric clock and transceiver reference clock domains.

Use Value: FS pin allows runtime switching between 300 MHz (compute) and 250 MHz (PCIe Gen4) frequencies without firmware reload.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output XO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si544AA001038BBG	Single-output variant of same Si54x family; identical jitter (80 fs), stability (±7 ppm), and package; lacks second frequency path and FS pin control.	Applicable only where one clock domain suffices; cannot replace dual-frequency requirement of 546CAA001038BBG.	Select when system needs identical performance but only one output frequency - reduces cost and pin count where dual-frequency is unnecessary.
DS3232M-546CAA001038BBG	Not a valid alternative; DS3232M is a temperature-compensated RTC, not a programmable XO; no frequency agility, no dual output, >1000× higher jitter.	RTC timing vs. high-speed clock generation; incompatible signal integrity, jitter, and interface requirements.	Avoid - mismatched function class; no functional overlap in clock synthesis, jitter performance, or application scope.

Compared with Si544AA001038BBG, the 546CAA001038BBG adds FS-controlled dual-frequency capability at identical jitter and stability, enabling clock domain isolation in multi-protocol SoCs; compared with non-Si54x alternatives, it uniquely combines factory-programmable dual outputs, sub-100 fs jitter, and multi-voltage operation in one 5×7 mm package.

Availability

546CAA001038BBG is available at Aetrix Electronics and suitable for 100G/400G optical modules, high-speed Ethernet switches, broadcast video equipment, and FPGA-based compute accelerators requiring stable component supply with guaranteed long-term availability.

Supply support for 546CAA001038BBG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog components.

The Si546 Ultra Series™ is designed specifically for high-performance timing applications demanding ultra-low jitter, dual-frequency flexibility, and robust supply noise immunity in datacenter, telecom, and broadcast infrastructure.

FAQ

What is the factory-programmed frequency configuration of 546CAA001038BBG?

The 546CAA001038BBG is configured with two specific frequencies encoded in its six-digit frequency code "001038", which corresponds to 100.000000 MHz and 156.250000 MHz per Skyworks' official ordering guide. These values are permanently stored in on-chip NVM and cannot be field-reprogrammed. Both frequencies are fully supported across all output formats and operate within the device's specified jitter and stability limits.

Does 546CAA001038BBG support LVDS output at 156.25 MHz with guaranteed jitter performance?

Yes, 546CAA001038BBG supports LVDS output at 156.25 MHz with 90 fs typical RMS phase jitter (12 kHz–20 MHz), as confirmed in Table 2.2 of the Si546 datasheet. This value falls within the 80–110 fs range specified for LVPECL/LVDS/CML formats at ≥200 MHz, and the 156.25 MHz point is explicitly characterized with 90 fs typical performance in the same table.

What is the thermal resistance (ΘJA) of the 5×7 mm package used by 546CAA001038BBG?

The 5×7 mm 6-pin CLCC package of 546CAA001038BBG has a thermal resistance junction-to-ambient (ΘJA) of 53 °C/W under still-air conditions at 85 °C, per Table 2.5 in the Si546 datasheet. This value assumes a 4-layer, 1.6 mm thick PCB (4.5″ × 7″) and informs thermal design for sustained operation up to the 95 °C maximum operating temperature.

Can the OE/FS pin polarity of 546CAA001038BBG be changed after manufacturing?

No, the OE/FS pin polarity and pin assignment (Pin 1 or Pin 2) for 546CAA001038BBG are factory-programmed during final test and are immutable. The "A" in the ordering code "546CAA…" indicates active-high OE on Pin 1, as defined in Skyworks' Ordering Guide section 1. This configuration is laser-trimmed and stored in non-volatile memory; no external register or command can alter it.

Is 546CAA001038BBG compliant with RoHS and REACH regulations?

Yes, 546CAA001038BBG complies with RoHS Directive 2011/65/EU and REACH Regulation (EC) No. 1907/2006, as documented in Skyworks' corporate quality portal. Material declarations, including homogeneous substance thresholds and SVHC screening, are accessible via www.skyworksinc.com/quality under the "Corporate Request For Information" system using the full part number 546CAA001038BBG.

546CAA001038BBG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Ultra™ Si546

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 256kHz, 32MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 1.8V, 2.5V, 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 127mA

Ratings:: -

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height:: 0.052" (1.33mm)

Supplier Device Package:: -

546CAA001038BBG FAQ

1.How can I place an order for 546CAA001038BBG through Aetrix?

Please submit a Request for Quotation (RFQ) for 546CAA001038BBG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 546CAA001038BBG reliable?

The price and inventory of 546CAA001038BBG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 546CAA001038BBG is usually 5 days.

3.What payment methods are accepted for 546CAA001038BBG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 546CAA001038BBG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 546CAA001038BBG?

546CAA001038BBG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 546CAA001038BBG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 546CAA001038BBG?

For technical support, including 546CAA001038BBG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 546CAA001038BBG requirements.

6.How does Aetrix verify that 546CAA001038BBG is sourced from the original manufacturer or authorized distributors?

All 546CAA001038BBG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 546CAA001038BBG meets industry standards.

7.What is the process for return or replacement of 546CAA001038BBG?

All 546CAA001038BBG units undergo pre-shipment inspection (PSI). If there is an issue with 546CAA001038BBG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 546CAA001038BBG part is unused and in its original packaging.

Return procedure for 546CAA001038BBG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…