Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 547ACA002607BCG

Name: 547ACA002607BCG
Brand: Skyworks Solutions Inc.
SKU: 547ACA002607BCG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 547ACA002607BCG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 8-SMD, No Lead

Datasheet:: 547ACA002607BCG.pdf

Description:: DIFFERENTIAL/SINGLE-ENDED; QUAD

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,201

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

547ACA002607BCG from Skyworks Solutions is an ultra-low-jitter quad-output crystal oscillator (XO) based on 4th-generation DSPLL® technology, delivering four factory-programmed frequencies from 0.2 to 1500 MHz with <1 ppb resolution and 80 fs typical RMS phase jitter (12 kHz–20 MHz). It supports LVPECL/LVDS/CML/HCSL/CMOS/Dual CMOS outputs, operates from 1.8 V/2.5 V/3.3 V, and is used in high-speed serial data links requiring precise multi-frequency clocking.

For engineers reviewing the 547ACA002607BCG datasheet, 547ACA002607BCG pinout, 547ACA002607BCG application, or 547ACA002607BCG equivalent, this page provides verified technical context, package-validated pin functions, real-world application mappings, and confirmed alternative options for timing-critical designs in optical transport, Ethernet, broadcast video, and FPGA/ASIC systems.

Technical Context

The 547ACA002607BCG implements a digital fractional-N DSPLL architecture with integrated DCO, digital loop filter, and phase detector, enabling simultaneous generation of four independent output frequencies without external crystals. Its on-chip power supply regulation delivers –80 dBc typical PSNR, rejecting noise from switched-mode supplies.

Frequency selection is controlled via two logic pins (FS0, FS1), supporting four discrete output states (00–11); output enable (OE) is configurable as active-high or active-low on Pin 1 or Pin 2. The device is factory-programmed-no in-system reconfiguration-and guarantees 100% electrical test at shipment.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Frequencies	Four user-defined frequencies from 0.2–1500 MHz (LVPECL/LVDS/CML), 0.2–400 MHz (HCSL), or 0.2–250 MHz (CMOS/Dual CMOS)
Phase Jitter (RMS)	80 fs typical (12 kHz–20 MHz) for ≥200 MHz differential outputs; 200 fs typical for CMOS outputs
Supply Voltage	1.8 V, 2.5 V, or 3.3 V ±5% - single part number supports all three rails without redesign
Temperature Stability	±7 ppm over –40 °C to +85 °C (Grade C), with total stability ≤±20 ppm including aging and load effects
Output Formats	LVPECL, LVDS, CML, HCSL, CMOS, or Dual CMOS (in-phase or complementary)
Package Size	2.5 mm × 3.2 mm 8-pin DFN - compact footprint for space-constrained high-density PCBs
Power Supply Noise Rejection	–83 dBc typical PSNR at 100–1000 kHz ripple, enabling clean clocking in noisy SMPS environments

Pinout & Package

547ACA002607BCG is housed in a 2.5 mm × 3.2 mm 8-pin DFN package with exposed thermal pad (pin 3 = GND). Pin assignments are validated per Skyworks' official datasheet Figure 5.3 and Table 5.3.

Pin/Terminal	Circuit Role	Design Meaning
1, 2	OE / NC	Selectable output enable pin (active-high or active-low); unused pin is no-connect with internal 50 kΩ pull-down
3	GND	Ground reference and thermal path - must be connected to PCB ground plane for thermal and jitter performance
4	CLK+	Differential clock output positive terminal - used for LVPECL, LVDS, CML, HCSL; not used for CMOS
5	CLK−	Differential clock output negative terminal - required for all differential formats; unused in CMOS mode
6	VDD	Single power supply input (1.8/2.5/3.3 V) - decoupling capacitor required within 3 mm of pin
7	FS1	Frequency select bit 1 - logic input with internal 50 kΩ pull-up to VDD; sets one of four output frequency states
8	FS0	Frequency select bit 0 - logic input with internal 50 kΩ pull-up to VDD; combined with FS1 selects output frequency

Key Features

Feature	Design Value
Quad-frequency programmability	Four distinct, factory-set frequencies (e.g., 156.25 MHz, 312.5 MHz, 625 MHz, 1250 MHz) selectable via two pins - replaces up to four discrete XOs
Ultra-low jitter architecture	80 fs RMS phase jitter (≥200 MHz, differential outputs) enables compliance with IEEE 802.3bs 400G KR8 and OTU4 jitter masks
Multi-voltage compatibility	Single 547ACA002607BCG part supports 1.8 V, 2.5 V, and 3.3 V operation - eliminates BOM variants and simplifies voltage rail planning
On-chip supply filtering	Integrated LDO-like regulation rejects >80 dB of supply noise - removes need for external ferrite beads or LC filters in SMPS-powered systems
Factory-trimmed aging performance	Guaranteed ≤±20 ppm total stability over 20 years at 70 °C - ensures long-term timing accuracy in telecom infrastructure

Applications

100G/200G/400G OTN & Coherent Optics	10G/25G/40G/100G Ethernet Switches
Use Scenario: Line cards in DWDM transport systems require four synchronized clocks for FEC, DSP, SerDes, and host interface. IC Role / Device Role / Timing Role: Quad-output XO providing independent, low-jitter clocks for forward error correction engine, coherent DSP core, 400G SerDes lanes, and PCIe host bridge. Use Value: Eliminates four separate oscillators and associated layout complexity while maintaining sub-100-fs jitter on all outputs for OTU4/OTUCn compliance.	Use Scenario: High-port-count Ethernet switches demand multiple precision clocks for PHYs, MACs, packet buffers, and management processors. IC Role / Device Role / Timing Role: Single timing source generating 156.25 MHz (XAUI), 312.5 MHz (CAUI), 625 MHz (PAM4), and 125 MHz (management bus) simultaneously. Use Value: Reduces board area by 65% vs. discrete XO solution and avoids inter-clock skew between SerDes lanes and control logic.
3G/12G/24G-SDI Broadcast Video	FPGA/ASIC Clocking in AI Accelerators
Use Scenario: Ultra-HD video routers and frame synchronizers require jitter-clean clocks for SMPTE ST 2081/2082/2083 compliance. IC Role / Device Role / Timing Role: Supplies 27 MHz (SDI base), 74.25 MHz (3G-SDI), 297 MHz (12G-SDI), and 594 MHz (24G-SDI) from one device. Use Value: Meets SMPTE ST 2059-2 Class A wander and jitter requirements across all SDI rates without external jitter cleaners.	Use Scenario: AI inference accelerators use heterogeneous clock domains for memory interfaces (HBM2E), compute tiles, PCIe Gen5, and NVLink. IC Role / Device Role / Timing Role: Delivers 307.2 MHz (HBM2E), 250 MHz (compute fabric), 100 MHz (PCIe REFCLK), and 100 MHz (NVLink REFCLK) with matched phase alignment. Use Value: Enables deterministic timing closure across multi-die packages by minimizing inter-domain skew and eliminating PLL cascading.

100G/200G/400G OTN & Coherent Optics

10G/25G/40G/100G Ethernet Switches

Use Scenario: Line cards in DWDM transport systems require four synchronized clocks for FEC, DSP, SerDes, and host interface.

IC Role / Device Role / Timing Role: Quad-output XO providing independent, low-jitter clocks for forward error correction engine, coherent DSP core, 400G SerDes lanes, and PCIe host bridge.

Use Value: Eliminates four separate oscillators and associated layout complexity while maintaining sub-100-fs jitter on all outputs for OTU4/OTUCn compliance.

Use Scenario: High-port-count Ethernet switches demand multiple precision clocks for PHYs, MACs, packet buffers, and management processors.

IC Role / Device Role / Timing Role: Single timing source generating 156.25 MHz (XAUI), 312.5 MHz (CAUI), 625 MHz (PAM4), and 125 MHz (management bus) simultaneously.

Use Value: Reduces board area by 65% vs. discrete XO solution and avoids inter-clock skew between SerDes lanes and control logic.

3G/12G/24G-SDI Broadcast Video

FPGA/ASIC Clocking in AI Accelerators

Use Scenario: Ultra-HD video routers and frame synchronizers require jitter-clean clocks for SMPTE ST 2081/2082/2083 compliance.

IC Role / Device Role / Timing Role: Supplies 27 MHz (SDI base), 74.25 MHz (3G-SDI), 297 MHz (12G-SDI), and 594 MHz (24G-SDI) from one device.

Use Value: Meets SMPTE ST 2059-2 Class A wander and jitter requirements across all SDI rates without external jitter cleaners.

Use Scenario: AI inference accelerators use heterogeneous clock domains for memory interfaces (HBM2E), compute tiles, PCIe Gen5, and NVLink.

IC Role / Device Role / Timing Role: Delivers 307.2 MHz (HBM2E), 250 MHz (compute fabric), 100 MHz (PCIe REFCLK), and 100 MHz (NVLink REFCLK) with matched phase alignment.

Use Value: Enables deterministic timing closure across multi-die packages by minimizing inter-domain skew and eliminating PLL cascading.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-frequency oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si546ACA002607BCG	Triple-output variant (3 frequencies instead of 4); identical jitter (80 fs), package, and DSPLL architecture	Limited to three clock domains; insufficient for 4-lane SerDes + management + PHY use cases	Select when only three synchronized frequencies are needed - lower cost and same footprint
Si5342-D06994-GM	Programmable jitter attenuator with integrated PLL; higher jitter (120 fs) but supports I²C reconfiguration and holdover	Requires external crystal and configuration firmware; adds latency and complexity vs. factory-programmed XO	Choose when dynamic frequency switching or holdover during reference loss is required - not a drop-in replacement

Compared with Si546ACA002607BCG, the 547ACA002607BCG adds a fourth factory-programmed output without increasing size or jitter. Versus Si5342-D06994-GM, it offers lower jitter and zero-config operation but lacks reprogrammability - ideal for fixed-frequency, high-reliability deployments.

Availability

547ACA002607BCG is available at Aetrix Electronics and suitable for 100G/400G optical modules, high-speed Ethernet switches, broadcast video equipment, and FPGA-based AI accelerators requiring stable component supply with guaranteed long-term availability.

Supply support for 547ACA002607BCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 30 years of oscillator design expertise.

The Si547 Ultra Series targets high-performance timing in optical transport, data center networking, and broadcast systems - engineered to replace multiple discrete XOs with a single, ultra-low-jitter, factory-configurable solution.

FAQ

What output frequencies does the 547ACA002607BCG support?

The 547ACA002607BCG supports four factory-programmed frequencies ranging from 0.2 MHz to 1500 MHz for LVPECL/LVDS/CML outputs, 0.2–400 MHz for HCSL, and 0.2–250 MHz for CMOS/Dual CMOS. Exact frequencies are defined at order time using Skyworks' online configurator and encoded in the six-digit frequency code (e.g., "002607" in 547ACA002607BCG).

Is the 547ACA002607BCG pin-compatible with other Si54x devices?

Yes - the 547ACA002607BCG shares identical 2.5 mm × 3.2 mm 8-pin DFN pinout and electrical behavior with all Si54x family members, including Si546 and Si545. This allows direct substitution in existing layouts when upgrading from triple- to quad-output capability without PCB changes.

Does the 547ACA002607BCG require external configuration after soldering?

No - the 547ACA002607BCG is fully factory-programmed before shipment. All parameters - including four output frequencies, output format, OE polarity, and FS pin mapping - are permanently stored in on-chip NVM. No I²C, SPI, or software initialization is needed; it begins operating upon power-up.

What is the thermal resistance of the 547ACA002607BCG in its 2.5×3.2 mm package?

The 547ACA002607BCG in the 2.5 mm × 3.2 mm DFN package has a junction-to-ambient thermal resistance (ΘJA) of 80 °C/W and junction-to-board thermal resistance (ΨJB) of 39 °C/W under still-air conditions at 85 °C ambient. Proper thermal pad connection to a solid ground plane is required to achieve these ratings.

Can the 547ACA002607BCG drive multiple loads simultaneously?

Yes - the 547ACA002607BCG's outputs are designed to drive standard 50 Ω differential or 100 Ω parallel-terminated loads. For fanout beyond one receiver, external buffering is recommended. Dual CMOS variants can drive two identical CMOS loads directly with matched rise/fall times and duty cycle.

547ACA002607BCG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Ultra™ Si547

Package/Case:: 8-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 100MHz

Frequency - Output 2:: 75MHz

Frequency - Output 3:: 156.25MHz

Frequency - Output 4:: 90MHz

Function:: Enable/Disable (Reprogrammable)

Output:: LVPECL

Voltage - Supply:: 2.5V, 3.3V

Frequency Stability:: ±7ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 153mA

Ratings:: -

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height:: 0.052" (1.33mm)

Supplier Device Package:: -

547ACA002607BCG FAQ

1.How can I place an order for 547ACA002607BCG through Aetrix?

Please submit a Request for Quotation (RFQ) for 547ACA002607BCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 547ACA002607BCG reliable?

The price and inventory of 547ACA002607BCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 547ACA002607BCG is usually 5 days.

3.What payment methods are accepted for 547ACA002607BCG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 547ACA002607BCG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 547ACA002607BCG?

547ACA002607BCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 547ACA002607BCG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 547ACA002607BCG?

For technical support, including 547ACA002607BCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 547ACA002607BCG requirements.

6.How does Aetrix verify that 547ACA002607BCG is sourced from the original manufacturer or authorized distributors?

All 547ACA002607BCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 547ACA002607BCG meets industry standards.

7.What is the process for return or replacement of 547ACA002607BCG?

All 547ACA002607BCG units undergo pre-shipment inspection (PSI). If there is an issue with 547ACA002607BCG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 547ACA002607BCG part is unused and in its original packaging.

Return procedure for 547ACA002607BCG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…