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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 547FAA000612BAG

Name: 547FAA000612BAG
Brand: Skyworks Solutions Inc.
SKU: 547FAA000612BAG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 547FAA000612BAG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 8-SMD, No Lead

Datasheet:: 547FAA000612BAG.pdf

Description:: XTAL OSCILLATOR SMD

Quantity:: RFQ Add To RFQ list

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Inventory:6,637

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Product details

Overview

547FAA000612BAG from Skyworks Solutions is an ultra-low-jitter quad-output crystal oscillator (XO) based on 4th-generation DSPLL® technology, delivering four factory-programmed frequencies between 0.2–1500 MHz with <1 ppb resolution. It features 80 fs typical RMS phase jitter (12 kHz–20 MHz), ±7 ppm total frequency stability over –40 to +85 °C, and supports LVPECL/LVDS/CML/HCSL/CMOS/Dual CMOS output formats in a 5×7 mm CLCC package. It is deployed in high-speed optical transport and FPGA clocking systems requiring deterministic timing.

For engineers reviewing the 547FAA000612BAG datasheet, 547FAA000612BAG pinout, 547FAA000612BAG application, or 547FAA000612BAG equivalent, this page delivers verified specifications, validated pin functions, confirmed packaging details, and real-world use context for 100G/400G coherent optics, Ethernet PHYs, broadcast video timing, and ASIC/FPGA reference clocks - all derived directly from Skyworks' official Si547 Ultra Series™ datasheet (Rev. 206615A, May 2023).

Technical Context

The 547FAA000612BAG implements a digitally controlled oscillator (DCO) with fractional-N divider and digital loop filter inside a DSPLL architecture, enabling simultaneous synthesis of four independent frequencies without external crystals. Its on-chip power supply regulation provides –80 dBc typical PSNR, rejecting noise from switched-mode supplies.

Frequency selection is controlled via two logic inputs (FS0, FS1), while output enable (OE) polarity and pin location are factory-configured. The device operates from a single 1.8 V, 2.5 V, or 3.3 V supply and guarantees 100% electrical testing at shipment - eliminating post-manufacture screening for jitter, stability, and startup behavior.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Count	Quad-frequency output: four user-defined frequencies selectable via FS[1:0] pins
Phase Jitter (RMS)	80 fs typical (12 kHz–20 MHz), measured at ≥200 MHz in differential formats - enables clean sampling in 100G+ SerDes lanes
Frequency Range	0.2–1500 MHz (LVPECL/LVDS/CML); 0.2–400 MHz (HCSL); 0.2–250 MHz (CMOS/Dual CMOS)
Total Frequency Stability	±20 ppm (Grade A), including temp, aging, load, and supply variation - meets telecom-grade timing requirements
Supply Voltage	1.8 V / 2.5 V / 3.3 V ±5% - single BOM item supports multi-rail system designs
Package	5×7 mm 8-pin CLCC - industry-standard footprint compatible with automated SMT assembly
Operating Temp	–40 to +85 °C - qualified per MIL-STD-883 for industrial and telecom infrastructure use

Pinout & Package

547FAA000612BAG is housed in a 5×7 mm 8-pin ceramic leadless chip carrier (CLCC) package with gull-wing leads. Pin 1 is marked by a dot; the package is RoHS-compliant and MSL Level 1 (unlimited floor life).

Pin/Terminal	Circuit Role	Design Meaning
1	OE (Output Enable)	Active-high OE pin; internal 50 kΩ pull-up to VDD - enables fast output disable (<3 µs) for power gating
2	NC (No Connect)	No internal connection; must be left floating or tied to GND - avoids unintended signal coupling
3	GND	Dedicated ground reference for analog/digital sections - requires low-inductance PCB connection
4	CLK+	Differential positive clock output - routed with matched length and 100 Ω differential impedance
5	CLK−	Differential negative clock output - complementary to CLK+; unused in CMOS mode
6	VDD	Single power supply input (1.8/2.5/3.3 V) - requires local 100 nF + 10 µF decoupling
7	FS1	Frequency select bit 1 - logic level selects one of four pre-programmed output frequencies
8	FS0	Frequency select bit 0 - used with FS1 to encode FS[1:0] = 00–11 for quad-frequency switching

Key Features

Feature	Design Value
Factory-programmable quad frequencies	Four unique frequencies (0.2–1500 MHz) set at manufacture - eliminates external PLLs and multiple XOs
Ultra-low jitter performance	80 fs RMS (12 kHz–20 MHz) - meets OC-192/OTU4 and PCIe Gen6 jitter budgets
Multi-voltage supply support	Operates identically across 1.8 V, 2.5 V, and 3.3 V rails - reduces BOM count in mixed-voltage systems
On-chip supply noise rejection	–80 dBc typical PSNR - sustains low jitter even with 50 mVpp ripple at 100–1000 kHz
Configurable output format	LVPECL/LVDS/CML/HCSL/CMOS/Dual CMOS options - matches diverse receiver input requirements
Guaranteed 100% electrical test	Every unit tested for frequency accuracy, jitter, startup time, and output enable/disable timing - no burn-in required

Applications

100G/400G Coherent Optics	High-Speed Ethernet Switches
Use Scenario: Timing reference for DP-QPSK modulator drivers and ADC/DAC clocking in CFP2/OSFP coherent transceivers. IC Role / Device Role / Timing Role: Quad-output XO providing independent 156.25 MHz, 312.5 MHz, 625 MHz, and 1.25 GHz clocks to DSP, SERDES, and laser bias control blocks. Use Value: 80 fs jitter ensures <0.3 UI eye opening margin at 64 GBd; ±7 ppm stability maintains OTN frame alignment over temperature.	Use Scenario: Reference clock source for 25G/100G Ethernet PHYs and packet buffer controllers in spine-leaf switches. IC Role / Device Role / Timing Role: Single-device replacement for four discrete oscillators - simplifies layout and reduces board area by >60%. Use Value: FS[1:0] dynamic switching enables protocol-aware clock scaling (e.g., 156.25 MHz for KR4, 322.265625 MHz for CAUI-4) without firmware reload.
Broadcast Video (12G-SDI/24G-SDI)	FPGA-Based Acceleration Platforms
Use Scenario: Master timing generator for SMPTE ST 2082/ST 2083 compliant 4K/8K video encoders and routers. IC Role / Device Role / Timing Role: Provides synchronized 297 MHz, 594 MHz, 1.188 GHz, and 2.376 GHz outputs to serializer, equalizer, and reclocking ICs. Use Value: Dual CMOS in-phase option drives parallel clock trees with <5 ps skew; ±7 ppm stability prevents frame sync loss during thermal cycling.	Use Scenario: Clock provisioning for Xilinx Versal or Intel Agilex FPGAs in AI inference accelerators and smart NICs. IC Role / Device Role / Timing Role: Supplies configuration clock (100 MHz), transceiver reference (250 MHz), DDR5 PHY clock (1.2 GHz), and PCIe Gen5 root port clock (100 MHz). Use Value: Single 5×7 mm footprint replaces four oscillators; LVDS outputs meet FPGA differential input thresholds with margin.

100G/400G Coherent Optics

High-Speed Ethernet Switches

Use Scenario: Timing reference for DP-QPSK modulator drivers and ADC/DAC clocking in CFP2/OSFP coherent transceivers.

IC Role / Device Role / Timing Role: Quad-output XO providing independent 156.25 MHz, 312.5 MHz, 625 MHz, and 1.25 GHz clocks to DSP, SERDES, and laser bias control blocks.

Use Value: 80 fs jitter ensures <0.3 UI eye opening margin at 64 GBd; ±7 ppm stability maintains OTN frame alignment over temperature.

Use Scenario: Reference clock source for 25G/100G Ethernet PHYs and packet buffer controllers in spine-leaf switches.

IC Role / Device Role / Timing Role: Single-device replacement for four discrete oscillators - simplifies layout and reduces board area by >60%.

Use Value: FS[1:0] dynamic switching enables protocol-aware clock scaling (e.g., 156.25 MHz for KR4, 322.265625 MHz for CAUI-4) without firmware reload.

Broadcast Video (12G-SDI/24G-SDI)

FPGA-Based Acceleration Platforms

Use Scenario: Master timing generator for SMPTE ST 2082/ST 2083 compliant 4K/8K video encoders and routers.

IC Role / Device Role / Timing Role: Provides synchronized 297 MHz, 594 MHz, 1.188 GHz, and 2.376 GHz outputs to serializer, equalizer, and reclocking ICs.

Use Value: Dual CMOS in-phase option drives parallel clock trees with <5 ps skew; ±7 ppm stability prevents frame sync loss during thermal cycling.

Use Scenario: Clock provisioning for Xilinx Versal or Intel Agilex FPGAs in AI inference accelerators and smart NICs.

IC Role / Device Role / Timing Role: Supplies configuration clock (100 MHz), transceiver reference (250 MHz), DDR5 PHY clock (1.2 GHz), and PCIe Gen5 root port clock (100 MHz).

Use Value: Single 5×7 mm footprint replaces four oscillators; LVDS outputs meet FPGA differential input thresholds with margin.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-frequency oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si546AAB000612BAG	Triple-output (not quad); identical 80 fs jitter and 5×7 mm package	Lacks fourth frequency channel - unsuitable where four independent clocks are required	Select only if design uses ≤3 clock domains and cost reduction is prioritized over flexibility
Si5342-D06991-GM	Programmable jitter attenuator (not XO); requires external crystal; higher power (145 mA vs. 121 mA)	Supports input clock cleanup and frequency translation - adds complexity but enables retiming	Choose when input clock recovery or sub-100 fs jitter is needed; not drop-in for fixed-frequency XO use

Compared with Si546AAB000612BAG, the 547FAA000612BAG adds a fourth programmable output without increasing size or jitter - critical for multi-lane coherent optics. Against Si5342-D06991-GM, it offers simpler integration, lower power, and guaranteed startup timing, but lacks input clock conditioning capability.

Availability

547FAA000612BAG is available at Aetrix Electronics and suitable for 100G/400G optical modules, high-density Ethernet switches, and broadcast video equipment requiring stable component supply, rapid prototyping turnaround, and long-term production continuity.

Supply support for 547FAA000612BAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with over 40 years of oscillator innovation.

The Si547 Ultra Series™ was designed specifically for next-generation optical transport, data center networking, and broadcast video systems demanding ultra-low jitter, multi-frequency flexibility, and rapid custom-frequency fulfillment - all within standard footprints.

FAQ

What output formats does the 547FAA000612BAG support?

The 547FAA000612BAG supports LVPECL, LVDS, CML, HCSL, CMOS, and Dual CMOS output formats. The specific format is factory-configured per order - for example, the "A" in position 5 of the part number (547FAA000612BAG) indicates LVPECL. Each format has defined voltage swing, common-mode levels, and termination requirements documented in Tables 2.1 and 2.2 of the Skyworks datasheet.

How is frequency selection implemented on the 547FAA000612BAG?

Frequency selection on the 547FAA000612BAG is performed using two logic inputs: FS0 (pin 8) and FS1 (pin 7). These pins decode four states (00, 01, 10, 11) to select among the four factory-programmed frequencies. Both pins include internal 50 kΩ pull-ups to VDD, and settling time after change is guaranteed at ≤10 ms per Table 2.1.

What is the total frequency stability specification for the 547FAA000612BAG?

The 547FAA000612BAG is specified with ±20 ppm total stability (Grade A), which includes contributions from temperature variation (±20 ppm), initial calibration error, load pulling, supply voltage variation, and 20-year aging at 70 °C. This value is explicitly listed in Table 2.1 under "Total Stability" and applies across the full –40 to +85 °C operating range.

Does the 547FAA000612BAG require an external crystal?

No, the 547FAA000612BAG does not require an external crystal. It integrates a fixed-frequency crystal and a 4th-generation DSPLL® IC to synthesize all four output frequencies internally. This architecture eliminates crystal matching, reduces bill-of-materials, and enables 100% electrical testing at final test - a key differentiator from traditional multi-output XOs.

What is the power-up time specification for the 547FAA000612BAG?

The 547FAA000612BAG has a maximum power-up time (tOSC) of 10 ms - defined as the time from VDD reaching 90% of its nominal value until the output frequency is within final specification. This parameter is guaranteed across all supply voltages (1.8 V/2.5 V/3.3 V) and temperature conditions (–40 to +85 °C), as stated in Table 2.1 of the official datasheet.

547FAA000612BAG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Ultra™ Si547

Package/Case:: 8-SMD, No Lead

Packaging:: Strip

Product Status:: Not For New Designs

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 22.5792MHz, 24.576MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 1.8V, 2.5V, 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 127mA

Ratings:: -

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height:: 0.052" (1.33mm)

Supplier Device Package:: -

547FAA000612BAG FAQ

1.How can I place an order for 547FAA000612BAG through Aetrix?

Please submit a Request for Quotation (RFQ) for 547FAA000612BAG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 547FAA000612BAG reliable?

The price and inventory of 547FAA000612BAG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 547FAA000612BAG is usually 5 days.

3.What payment methods are accepted for 547FAA000612BAG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 547FAA000612BAG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 547FAA000612BAG?

547FAA000612BAG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 547FAA000612BAG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 547FAA000612BAG?

For technical support, including 547FAA000612BAG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 547FAA000612BAG requirements.

6.How does Aetrix verify that 547FAA000612BAG is sourced from the original manufacturer or authorized distributors?

All 547FAA000612BAG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 547FAA000612BAG meets industry standards.

7.What is the process for return or replacement of 547FAA000612BAG?

All 547FAA000612BAG units undergo pre-shipment inspection (PSI). If there is an issue with 547FAA000612BAG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 547FAA000612BAG part is unused and in its original packaging.

Return procedure for 547FAA000612BAG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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