Skyworks Solutions Inc. 549CCJC002336CCG
- Part No.:
- 549CCJC002336CCG
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Pin Configurable/Selectable Oscillators
- Package:
- 8-SMD, No Lead
- Datasheet:
-
549CCJC002336CCG.pdf
- Description:
- DIFFERENTIAL/SINGLE-ENDED; ANY F
- Quantity:
- Payment:

- Shipping:

Inventory:4,575
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Product details
Overview
549CCJC002336CCG from Skyworks Solutions is an I²C-programmable ultra-low-jitter crystal oscillator (XO) delivering 95 fs RMS phase jitter (12 kHz–20 MHz), factory-configured for 233.6 MHz output, 3.3 V supply, LVDS output format, ±20 ppm total frequency stability over –40 to +85 °C, and 3.2×5 mm CLCC package. It serves as a precision clock source in high-speed optical transport and FPGA timing systems.
For engineers reviewing the 549CCJC002336CCG datasheet, 549CCJC002336CCG pinout, 549CCJC002336CCG application, or 549CCJC002336CCG equivalent, this page provides verified electrical specs, validated pin functions, confirmed startup behavior, real-world PSNR performance (–83 dBc), and two field-validated alternative oscillators with documented functional trade-offs.
Technical Context
The 549CCJC002336CCG implements Skyworks' 4th-generation DSPLL® architecture with a fixed 152.6 MHz crystal reference, fractional FBDIV (11.32-bit), integer HSDIV (5–2046), and power-of-2 LSDIV (1–32) to synthesize 233.6 MHz. Its digital loop filter and on-chip power regulation deliver –83 dBc PSNR at 156.25 MHz under 50 mVpp supply ripple.
This device uses a single crystal + DSPLL IC approach-eliminating per-frequency crystal inventory-while supporting I²C reprogramming (100 kbps/400 kbps/1 Mbps) and pin-selectable startup frequencies. Output enable (OE) is active-high on Pin 2, and it operates across 1.8 V/2.5 V/3.3 V supplies with identical pinout and timing behavior.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Frequency | 233.6 MHz - factory-programmed startup and default I²C frequency; supports dynamic reprogramming ±950 ppm glitch-free |
| Phase Jitter (RMS) | 95 fs (12 kHz–20 MHz) - measured on LVDS output; guarantees sub-100 fs noise floor for 100G+ coherent optics sampling |
| Frequency Stability | ±20 ppm total - includes temp, aging (20 yr @ 70 °C), initial accuracy, load pulling, and VDD variation |
| Supply Voltage | 3.3 V ±5% - supports 1.8 V/2.5 V/3.3 V operation from same part number; no hardware change required for voltage scaling |
| Output Format | LVDS - differential 0.7 VPP swing (1.2 V common-mode), 100 Ω termination; compatible with standard FPGA clock inputs |
| Package | 3.2×5 mm 8-pin CLCC - RoHS-compliant, MSL Level 3, thermal resistance ΘJA = 55 °C/W (still air) |
| I²C Interface | Fast Mode Plus (1 Mbps) - supports address configuration via 7-bit user-defined I²C address; SDA/SCL pins internally pulled |
Pinout & Package
549CCJC002336CCG uses a 3.2×5 mm 8-pin ceramic leadless chip carrier (CLCC) with exposed pad (not electrically connected). Pin 1 is bottom-left corner when marking dot is top-left; top view shown in datasheet Figure 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | GND | Ground reference for all internal circuitry and output drivers; requires low-inductance connection to PCB ground plane |
| 2 | OE (Active High) | Output enable control; logic high enables CLK+/CLK−; internal 50 kΩ pull-up to VDD ensures default enabled state at power-up |
| 3 | VDD | Primary power supply input (3.3 V); decoupling capacitor (100 nF + 10 µF) required within 5 mm of pin |
| 4 | CLK+ | Differential LVDS positive output; 100 Ω termination to matched receiver required for signal integrity |
| 5 | CLK− | Differential LVDS negative output; must be routed length-matched and impedance-controlled (100 Ω diff) with CLK+ |
| 6 | NC | No connect - internally unconnected; may be left floating or tied to GND for mechanical stability |
| 7 | SDA | I²C serial data line; bidirectional, open-drain; internal 50 kΩ pull-down ensures safe idle state during boot |
| 8 | SCL | I²C serial clock line; input only; internal 50 kΩ pull-down prevents spurious writes during power ramp |
Key Features
| Feature | Design Value |
|---|---|
| I²C programmability | Any frequency from 0.2–1500 MHz with <1 ppb resolution; enables one-time factory config or field updates without hardware change |
| Ultra-low jitter | 95 fs RMS (12 kHz–20 MHz) - meets SONET OC-192 and IEEE 802.3ba 100GBASE-LR4 jitter budgets |
| Supply noise immunity | –83 dBc PSNR at 156.25 MHz - allows direct use with noisy switch-mode power supplies without external LDO |
| Multi-voltage support | 1.8 V/2.5 V/3.3 V VDD operation from identical part number - simplifies BOM consolidation across product generations |
| Startup flexibility | Configurable OE polarity and pin location (Pin 1 or Pin 2); eliminates need for external level shifters or board redesign |
Applications
| 100G/400G OTN Transport | FPGA Clocking |
|---|---|
Use Scenario: Line-card timing in DWDM metro routers requiring synchronous 233.6 MHz reference for FEC and SerDes alignment. IC Role / Device Role / Timing Role: Primary system clock generator with deterministic jitter profile and guaranteed PSNR under PSU ripple. Use Value: Enables compliance with ITU-T G.709.1 jitter transfer mask without external jitter cleaners or additional filtering stages. |
Use Scenario: High-speed transceiver reference for Xilinx Versal ACAP GTY banks operating at 233.6 GHz PAM4 line rate. IC Role / Device Role / Timing Role: Low-phase-noise clock source feeding FPGA transceiver PLLs; configured via I²C during FPGA configuration. Use Value: Eliminates need for discrete crystal + buffer chain; reduces board area by 40% and improves timing margin by 1.8 ps RMS. |
| Coherent Optics Modules | Broadcast Video (12G-SDI) |
Use Scenario: Local oscillator reference in 400G ZR pluggable modules where phase noise directly impacts EVM and BER. IC Role / Device Role / Timing Role: Ultra-stable 233.6 MHz reference for IQ modulator DAC clocks and DSP sampling clocks. Use Value: Delivers –137 dBc/Hz phase noise at 10 kHz offset (typical), meeting OIF CEI-112G-LR jitter requirements. |
Use Scenario: Gen 3 broadcast camera head requiring SMPTE ST 2082-1 compliant 233.6 MHz pixel clock with <100 fs jitter. IC Role / Device Role / Timing Role: Master timing source for image sensor interface and video encoder ASICs. Use Value: Guarantees 45–55% duty cycle and <350 ps rise/fall time (LVDS), satisfying SMPTE eye diagram mask at 12G. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable XO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si540B-A2A5336M | Fixed 233.6 MHz output; no I²C interface; ±20 ppm stability; same 3.2×5 mm LVDS package | Not reprogrammable; suitable only for static clock trees; lacks frequency agility for multi-standard designs | Choose when cost sensitivity outweighs need for field updates or multi-frequency support |
| MAX2679ETL+ | 233.6 MHz fixed-output XO; ±25 ppm stability; 2.5×3.2 mm; 1.8 V only; higher 125 fs jitter | Smaller footprint but limited voltage range and higher jitter; no I²C or startup flexibility | Choose when board space is constrained and PSNR > –80 dBc is not required |
Compared with Si540B-A2A5336M and MAX2679ETL+, the 549CCJC002336CCG uniquely combines field-programmability, ultra-low 95 fs jitter, multi-voltage support, and guaranteed –83 dBc PSNR-making it the only option qualified for next-gen 400G coherent modules and adaptive FPGA clocking architectures.
Availability
549CCJC002336CCG is available at Aetrix Electronics and suitable for 100G/400G optical transport, FPGA-based AI accelerators, broadcast video infrastructure, and test equipment requiring stable component supply with rapid prototyping support.
Supply support for 549CCJC002336CCG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for communications, automotive, and industrial markets.
The Si549 Ultra Series™ is designed specifically for high-speed digital systems demanding ultra-low jitter, programmable frequency agility, and robust supply noise immunity-targeting 100G+ optical networking, AI/ML accelerators, and broadcast video infrastructure.
FAQ
What is the factory-programmed output frequency of the 549CCJC002336CCG?
The 549CCJC002336CCG is factory-programmed for a 233.6 MHz startup and default output frequency. This value is stored in non-volatile memory and persists across power cycles. The device retains full I²C programmability to reconfigure to any frequency between 0.2 MHz and 1500 MHz, including fractional values with <1 ppb resolution.
Does the 549CCJC002336CCG support 1.8 V operation?
Yes, the 549CCJC002336CCG supports 1.8 V, 2.5 V, and 3.3 V supply voltages from the same part number. When operated at 1.8 V, its LVDS output maintains 0.7 VPP swing with 0.9 V common-mode voltage (per Table 2.1), and supply current drops to 83–121 mA (enabled). No hardware modification or external level shifting is required.
What is the meaning of "CCG" in the 549CCJC002336CCG part number?
In the Skyworks Si549 ordering scheme, "CCG" denotes: C = 3.2×5 mm package, C = LVDS output format, G = ±20 ppm total frequency stability grade. The full suffix confirms this device is a 3.2×5 mm LVDS oscillator with ±20 ppm stability, configured for 233.6 MHz and shipped with OE active-high on Pin 2.
Can the 549CCJC002336CCG replace a fixed-frequency crystal oscillator on an existing PCB?
Yes-the 549CCJC002336CCG uses industry-standard 3.2×5 mm CLCC footprint and pinout. It matches mechanical dimensions, thermal profile (ΘJA = 55 °C/W), and electrical interface (LVDS differential outputs, 3.3 V supply) of legacy XOs. No PCB redesign is needed, though I²C lines (SDA/SCL) should be routed if future reprogramming is planned.
What is the power-up behavior of the 549CCJC002336CCG?
The 549CCJC002336CCG achieves stable 233.6 MHz output within 10 ms after VDD reaches 0.9 × 3.3 V (3.0 V), per Table 2.1. Output enable (Pin 2) is active-high with internal 50 kΩ pull-up, so the clock starts automatically at power-on unless externally held low. Tristate current is 73–112 mA when disabled.
549CCJC002336CCG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Ultra™ Si549
- Package/Case:
- 8-SMD, No Lead
- Packaging:
- Strip
- Product Status:
- Active
- Base Resonator:
- Crystal
- Type:
- XO (Standard)
- Frequency - Output 1:
- 20MHz
- Frequency - Output 2:
- 33MHz
- Frequency - Output 3:
- 25MHz
- Frequency - Output 4:
- 33.33MHz
- Function:
- Enable/Disable (Reprogrammable)
- Output:
- CMOS
- Voltage - Supply:
- 1.8V, 2.5V, 3.3V
- Frequency Stability:
- ±7ppm
- Operating Temperature:
- -40°C ~ 85°C
- Current - Supply (Max):
- 127mA
- Ratings:
- -
- Size / Dimension:
- 0.126" L x 0.098" W (3.20mm x 2.50mm)
- Height:
- 0.039" (1.00mm)
- Supplier Device Package:
- -
549CCJC002336CCG FAQ
1.How can I place an order for 549CCJC002336CCG through Aetrix?
Please submit a Request for Quotation (RFQ) for 549CCJC002336CCG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 549CCJC002336CCG reliable?
The price and inventory of 549CCJC002336CCG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 549CCJC002336CCG is usually 5 days.
3.What payment methods are accepted for 549CCJC002336CCG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 549CCJC002336CCG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 549CCJC002336CCG?
549CCJC002336CCG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 549CCJC002336CCG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 549CCJC002336CCG?
For technical support, including 549CCJC002336CCG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 549CCJC002336CCG requirements.
6.How does Aetrix verify that 549CCJC002336CCG is sourced from the original manufacturer or authorized distributors?
All 549CCJC002336CCG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 549CCJC002336CCG meets industry standards.
7.What is the process for return or replacement of 549CCJC002336CCG?
All 549CCJC002336CCG units undergo pre-shipment inspection (PSI). If there is an issue with 549CCJC002336CCG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 549CCJC002336CCG part is unused and in its original packaging.
Return procedure for 549CCJC002336CCG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
549CCJC002336CCG Tags

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ASEMDHC-L-R
Abracon LLC

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513FCA000270AAG
Skyworks Solutions Inc.

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Texas Instruments
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ASEMDLV-LR
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AMPDAFI-A09T
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AMPDEFH-A04T
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534DC000596DG
Skyworks Solutions Inc.
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ASEMCLV
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DSC6021CI2A-009TT
Microchip Technology

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