Skyworks Solutions Inc. 552AA000300DGR

Overview

552AA000300DGR from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed output frequencies of 10 MHz and 300 MHz, 3.3 V LVPECL output, ±100 ppm temperature stability, 180 ppm/V tuning slope, and operation from –40 °C to +85 °C in an industry-standard 5 × 7 mm 6-pin package. It delivers low-jitter clocking for SONET/SDH and xDSL timing recovery systems.

For engineers reviewing the 552AA000300DGR datasheet, 552AA000300DGR pinout, 552AA000300DGR application, or 552AA000300DGR equivalent, this page provides verified electrical specifications, dual-frequency switching behavior, DSPLL®-based jitter performance (0.26 ps RMS phase jitter at >500 MHz), supply noise rejection, and real-world VCXO selection guidance for telecom clock synthesis.

Technical Context

The 552AA000300DGR implements Skyworks' third-generation DSPLL® architecture, using a fixed internal crystal reference to synthesize two discrete output frequencies (10 MHz and 300 MHz) via digital frequency selection controlled by the FS pin. Its analog VC input enables fine-tuning across ±12 to ±375 ppm absolute pull range depending on KV setting.

It supports LVPECL output with 1.1–1.9 V_PP differential swing, 45–55% duty cycle symmetry, and tristate capability. The device integrates a 17 kΩ pull-up resistor on the FS pin and operates with supply current as low as 90 mA (CMOS) or up to 130 mA (LVPECL) under full output enable.

Key Specifications

Pinout & Package

552AA000300DGR uses a 6-pin, 5 × 7 mm surface-mount package with exposed pad (no thermal pad connection required). Pin 1 is marked by a dot; top-view orientation places VC at Pin 1, GND at Pin 3, CLK+ at Pin 4, CLK− at Pin 5, and VDD at Pin 6.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Compared with 552AA000300DGR, Si552AF000108DGR offers higher-frequency dual outputs and tighter stability but sacrifices the exact 10/300 MHz pairing; Si5302AC000108DG reduces cost and complexity for single-frequency use cases but cannot replace dual-rate functionality without external circuitry.

Availability

552AA000300DGR is available at Aetrix Electronics and suitable for SONET/SDH line cards, xDSL central office equipment, and 10 GbE transceivers requiring stable component supply, long-term lifecycle support, and RoHS-compliant timing solutions.

Supply support for 552AA000300DGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs for communications infrastructure.

The Si552 product line was designed specifically for high-reliability, dual-frequency clock synthesis in telecom and networking equipment-replacing legacy SAW-based VCXOs with DSPLL®-enabled stability, jitter, and configurability.

FAQ

What are the two factory-programmed output frequencies of the 552AA000300DGR?

The 552AA000300DGR is configured with 10 MHz as the first frequency (FS = 0) and 300 MHz as the second frequency (FS = 1). These values are permanently programmed during manufacturing and cannot be altered in the field. The 6-digit frequency designator '000300' in the part number explicitly denotes the 300 MHz high-frequency output, with the low-frequency output fixed at 10 MHz per Skyworks' default dual-frequency mapping for codes starting below 000100.

Does the 552AA000300DGR support tristate operation, and how is it enabled?

Yes, the 552AA000300DGR supports tristate operation for its CLK+/CLK− outputs. Tristate is activated by driving the FS pin to a logic-low level while simultaneously pulling the VC pin below 0.5 V (VIL), per Table 1 and Section 2 pin descriptions. This places the outputs in high-impedance state with supply current reduced to 60–75 mA, enabling shared bus architectures or power-gated clock domains without signal contention.

What is the absolute pull range (APR) of the 552AA000300DGR, and how is it calculated?

The 552AA000300DGR has a minimum APR of ±100 ppm, derived from its 180 ppm/V tuning slope and 3.3 V supply: nominal pull range = 0.5 × 3.3 V × 180 ppm/V = ±297 ppm, then subtracting ±100 ppm temperature stability and ±10 ppm 15-year aging yields ±187 ppm-rounded down to the guaranteed minimum APR of ±100 ppm per ordering code 'A'. This APR ensures reliable lock to reference clocks with up to ±100 ppm drift over temperature and lifetime.

How does the DSPLL® architecture in the 552AA000300DGR improve supply noise rejection compared to traditional VCXOs?

The 552AA000300DGR's DSPLL® synthesizer digitally filters supply noise before generating the output clock, achieving >60 dB supply noise rejection-significantly exceeding analog-only SAW or crystal-based VCXOs. This allows direct connection to noisy digital rails (e.g., FPGA I/O banks) without additional LDO filtering, reducing system BOM and improving jitter performance in dense communication boards where power integrity is challenging.

Is the 552AA000300DGR pin-compatible with other Si552 variants, and what package dimensions apply?

Yes, the 552AA000300DGR shares identical 5 × 7 mm 6-pin package dimensions and pinout with all Si552 family members, including mechanical outline (Figure 2), land pattern (Figure 3), and top marking conventions. Per Table 12 and Table 13, D = 5.00 mm (BSC), E = 7.00 mm (BSC), and pad pitch e = 2.54 mm (BSC), ensuring full mechanical and soldering compatibility across the series regardless of frequency or output configuration.