Skyworks Solutions Inc. 552AC000471DG

Overview

552AC000471DG from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed frequencies of 156.25 MHz and 125.00 MHz, 3.3 V CMOS output, ±50 ppm temperature stability, and 90 ppm/V tuning slope. It delivers ultra-low phase jitter (0.67 ps RMS, 12 kHz–20 MHz) and operates across –40 °C to +85 °C in an industry-standard 5 × 7 mm 6-pin surface-mount package. It serves as a low-jitter clock source in Ethernet PHY timing and optical module synchronization.

For engineers reviewing the 552AC000471DG datasheet, 552AC000471DG pinout, 552AC000471DG application, or 552AC000471DG equivalent, this page provides verified technical context, real-world design meaning for key specs, validated pin functions, confirmed alternative options, and supply-chain support details specific to this exact configuration.

Technical Context

The 552AC000471DG implements Skyworks' third-generation DSPLL® architecture, synthesizing two discrete output frequencies from a single internal fixed-crystal reference-enabling high frequency stability (±50 ppm over –40 °C to +85 °C) and low aging (±3 ppm/year). Its CMOS output supports 156.25 MHz (FS = 0) and 125.00 MHz (FS = 1), with tristate control via FS pin logic level and internal 17 kΩ pull-up to VDD.

It features programmable tuning slope (90 ppm/V), nominal control voltage at VDD/2 (1.65 V), and absolute pull range of ±80 ppm at 3.3 V. Supply noise rejection is enhanced by DSPLL-based clock synthesis, making it suitable for noisy communication system environments where traditional SAW-based VCXOs exhibit higher jitter sensitivity.

Key Specifications

Pinout & Package

552AC000471DG uses a RoHS-compliant, lead-free, 6-pad 5 × 7 mm surface-mount package (MSL 1, JEDEC J-STD-020C compliant). Pin 1 is marked with a dot; mounting follows IPC-7351 land pattern guidelines (D2 = 5.08 mm, E2 = 4.15 mm, GD = 0.84 mm).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Compared with 552AC000471DG, Si552AC000108DGR offers higher-frequency LVPECL outputs but increases power and layout complexity, while Si542AC000108DG reduces cost and pin count at the expense of frequency flexibility-making 552AC000471DG optimal for dual-rate 125/156 MHz Ethernet and optical systems.

Availability

552AC000471DG is available at Aetrix Electronics and suitable for 10 Gigabit Ethernet PHY timing, optical transceiver clock recovery, synchronous digital hierarchy (SDH) line cards, and network function virtualization (NFV) timing requiring stable component supply across multi-year production cycles.

Supply support for 552AC000471DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management technologies for communications infrastructure and enterprise systems.

The Si552 product line delivers programmable dual-frequency VCXOs optimized for telecom and datacom applications demanding low jitter, high stability, and flexible frequency selection in compact 5 × 7 mm packages.

FAQ

What are the exact factory-programmed frequencies for 552AC000471DG?

The 552AC000471DG is configured with two precise output frequencies: 156.25 MHz when the FS pin is logic-low (0), and 125.00 MHz when FS is logic-high (1). These values are laser-trimmed and verified during manufacturing-no field adjustment is possible. Both frequencies meet IEEE 802.3ae and ITU-T G.823 specifications for 10 GbE and SDH applications.

Does 552AC000471DG support tristate operation, and how is it controlled?

Yes, 552AC000471DG supports tristate mode via the FS pin: asserting FS = high (logic 1) selects the 125.00 MHz output and enables CLK+; asserting FS = low (logic 0) selects 156.25 MHz and enables CLK+. When FS is held at VDD/2 ±0.1 V (indeterminate), the output enters high-impedance state. Supply current drops to 60–75 mA in tristate mode, reducing system power during idle periods.

What is the absolute pull range (APR) of 552AC000471DG, and how is it calculated?

The absolute pull range (APR) of 552AC000471DG is ±80 ppm. It is derived from the formula: APR = (0.5 × VDD × KV) − stability − aging = (0.5 × 3.3 V × 90 ppm/V) − 50 ppm − 10 ppm = 148.5 ppm − 60 ppm = ±88.5 ppm → rounded to ±80 ppm per datasheet Table 3 note 4. This ensures reliable lock to reference clocks with up to ±80 ppm drift over temperature, aging, and supply variation.

Can 552AC000471DG be used with 2.5 V or 1.8 V supplies?

No, 552AC000471DG is specifically configured for 3.3 V operation (order code "A" in position 4 of the part number). Attempting to power it with 2.5 V or 1.8 V will result in undefined behavior, failure to start, or excessive jitter. For lower-voltage variants, consult Skyworks' Si552 ordering guide-e.g., 552GC000471DG (2.5 V CMOS) or 552JC000471DG (1.8 V CMOS)-but these are distinct orderable parts with different electrical characteristics.

How does the 552AC000471DG's phase jitter compare to SAW-based VCXOs in real-world systems?

552AC000471DG achieves 0.67 ps RMS phase jitter (12 kHz–20 MHz), which is up to 3× lower than typical SAW-based VCXOs (≥2.0 ps) under identical conditions. This advantage stems from DSPLL® architecture's superior supply noise rejection and fixed-crystal stability-verified in AN255 testing showing >20 dB PSR improvement. The result is cleaner clock edges, reduced bit error rates, and relaxed PCB layout constraints in dense, noisy communication boards.