Skyworks Solutions Inc. 552AD000491DG

Overview

552AD000491DG from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed output frequencies of 100 MHz and 125 MHz, 3.3 V LVPECL output, ±50 ppm temperature stability, 90 ppm/V tuning slope, and operation from –40 to +85 °C in a 5 × 7 mm surface-mount package. It delivers low-jitter clock generation for SONET/SDH and 10 GbE LAN/WAN systems.

For engineers reviewing the 552AD000491DG datasheet, 552AD000491DG pinout, 552AD000491DG application, or 552AD000491DG equivalent, this page provides verified technical context, exact pin functions, jitter performance at specified KV and frequency points, dual-frequency switching behavior, and validated alternative VCXOs for telecom timing designs.

Technical Context

The 552AD000491DG implements Skyworks' third-generation DSPLL® architecture to synthesize two discrete output frequencies (100 MHz and 125 MHz) from a single internal fixed crystal reference. Its analog VC input accepts 0–VDD control voltage with 90 ppm/V tuning slope and supports ±12 to ±375 ppm absolute pull range depending on supply and configuration.

Frequency selection is performed via the digital FS pin, which toggles between the two preprogrammed outputs with ≤10 ms settling time. The device uses LVPECL differential outputs with 1.1–1.9 VPP swing, 45–55% duty cycle symmetry, and achieves 0.32 ps RMS phase jitter (12 kHz–20 MHz) at 125 MHz with KV = 90 ppm/V.

Key Specifications

Pinout & Package

552AD000491DG is housed in an industry-standard 5 × 7 mm, 6-pad surface-mount package with exposed pad thermal relief. Pin 1 is marked by a dot; top-side markings include "552", revision "D", and trace code.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Compared with 552AD000491DG, the Si550AC000108DG offers identical electrical specs but omits dual-frequency functionality, while the MAX2623EUA+ lacks integrated DSPLL, requires external components, and delivers significantly higher jitter-making the 552AD000491DG the only solution meeting OC-192-compliant dual-rate, low-jitter timing in a single 5 × 7 mm package.

Availability

552AD000491DG is available at Aetrix Electronics and suitable for SONET/SDH line cards, xDSL central office equipment, and 10 GbE LAN/WAN switches requiring stable component supply, long-lifecycle support, and RoHS-compliant timing devices.

Supply support for 552AD000491DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products.

The Si552 product line was designed specifically for high-reliability, low-jitter dual-frequency clock generation in telecom infrastructure, optical networking, and enterprise datacom systems where DSPLL-based stability and programmability are critical.

FAQ

What are the two factory-programmed output frequencies of the 552AD000491DG?

The 552AD000491DG is configured with 100 MHz as the first frequency (FS = 0) and 125 MHz as the second frequency (FS = 1). These values are permanently programmed at Skyworks' factory using the six-digit frequency designator "000491" per the Si552 ordering convention and cannot be modified in the field.

Does the 552AD000491DG support CMOS output format?

No, the 552AD000491DG does not support CMOS output. Its part number suffix "A" explicitly denotes 3.3 V LVPECL output format. CMOS is only available in variants with suffixes "C", "G", or "J", and is limited to frequencies ≤160 MHz.

What is the absolute pull range (APR) of the 552AD000491DG at 3.3 V supply?

With a 90 ppm/V tuning slope and ±50 ppm temperature stability, the 552AD000491DG achieves a minimum APR of ±80 ppm at 3.3 V. This is calculated as (0.5 × 3.3 V × 90 ppm/V) − 50 ppm − 10 ppm (aging), per Skyworks' APR definition in the datasheet.

How does the FS pin function on the 552AD000491DG?

The FS pin on the 552AD000491DG is a logic-controlled input with an internal 17 kΩ pull-up to VDD. When pulled low (≤0.5 V), it selects the first frequency (100 MHz); when high (≥0.75 × VDD), it selects the second (125 MHz). Settling time after FS transition is ≤10 ms.

Is the 552AD000491DG pin-compatible with other Si552 variants?

Yes, all Si552 variants-including 552AD000491DG-use the identical 5 × 7 mm, 6-pin package with standardized pinout (VC, FS, GND, CLK+, CLK−, VDD). Mechanical and electrical pin compatibility is guaranteed across the family, enabling drop-in replacement for different frequency or output format configurations.