Skyworks Solutions Inc. 552AD000736DG
- Part No.:
- 552AD000736DG
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Pin Configurable/Selectable Oscillators
- Package:
- 6-SMD, No Lead
- Datasheet:
-
552AD000736DG.pdf
- Description:
- XTAL OSC VCXO 3.3V 6SMD
- Quantity:
- Payment:

- Shipping:

Inventory:5,912
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
552AD000736DG from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed output frequencies of 125 MHz and 156.25 MHz, 3.3 V LVPECL output, ±50 ppm temperature stability, 90 ppm/V tuning slope, and operation from –40 to +85 °C in a 5 × 7 mm surface-mount package. It delivers ultra-low phase jitter (0.37 ps RMS, 12 kHz–20 MHz) for clock recovery in 10 GbE LAN/WAN systems.
For engineers reviewing the 552AD000736DG datasheet, 552AD000736DG pinout, 552AD000736DG application, or 552AD000736DG equivalent, this page provides verified electrical specs, dual-frequency switching behavior, DSPLL®-based supply noise rejection, and real-world timing performance data required for SONET/SDH and optical module design.
Technical Context
The 552AD000736DG implements Skyworks' third-generation DSPLL® architecture, using a fixed internal crystal reference to synthesize two discrete output frequencies (125 MHz and 156.25 MHz) via digital frequency selection controlled by the FS pin. Its analog VC input enables fine-tuning over ±100 ppm absolute pull range with 90 ppm/V slope.
Unlike SAW-based VCXOs, the 552AD000736DG achieves superior supply noise rejection and 3× better frequency stability due to its IC-based synthesis and internal fixed-crystal resonator. Output format is LVPECL, supporting differential signaling with 1.1–1.9 VPP swing and 45–55% duty cycle symmetry at 3.3 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Nominal Frequencies | 125 MHz (FS = 0), 156.25 MHz (FS = 1); enables dual-rate clocking without external PLL reconfiguration |
| Output Format | LVPECL; compatible with standard 50 Ω termination to VDD – 2.0 V, supports high-speed serial links |
| Tuning Slope (KV) | 90 ppm/V; allows ±100 ppm APR at 3.3 V while minimizing supply-induced jitter coupling |
| Phase Jitter (RMS) | 0.37 ps (12 kHz–20 MHz); meets OC-48/OC-192 timing budgets for 10 GbE and xDSL applications |
| Temperature Stability | ±50 ppm (–40 to +85 °C); ensures stable lock under industrial thermal cycling without recalibration |
| Supply Voltage | 3.3 V ±10%; supports legacy telecom power rails with 120–130 mA typical current draw |
| Aging (15-year) | ±10 ppm; guarantees long-term frequency accuracy in optical modules and base station timing |
Pinout & Package
552AD000736DG is housed in an industry-standard 6-pad, 5 × 7 mm surface-mount package (RoHS-compliant, Pb-free). Pin layout follows top-view orientation with Pin 1 marked by dot.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - VC | Analog control input | Accepts 0–VDD tuning voltage; sets output frequency within ±100 ppm APR window |
| 2 - FS | Digital frequency select | High = 156.25 MHz, Low = 125 MHz; includes internal 17 kΩ pull-up to VDD |
| 3 - GND | Ground reference | Common return for power, outputs, and control; requires low-inductance PCB connection |
| 4 - CLK+ | Differential output | LVPECL-compatible positive output; 1.1–1.9 VPP swing into 50 Ω load |
| 5 - CLK− | Differential output | Complementary LVPECL output; must be routed as matched-length pair for jitter control |
| 6 - VDD | Power supply | 3.3 V input; decoupling capacitor (0.1 µF + 10 µF) required within 5 mm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Dual-frequency selection | Hardware-switched between 125 MHz and 156.25 MHz via single FS pin-no I²C or configuration overhead |
| DSPLL® jitter suppression | 0.37 ps RMS phase jitter enables clean clock recovery in 10 GbE CDR circuits without external filtering |
| Fixed internal crystal | Eliminates aging and stability drift associated with external crystals; supports 15-year ±10 ppm aging spec |
| Supply noise rejection | Superior PSR vs. SAW VCXOs allows placement near noisy DC/DC converters in compact line cards |
| Industry-standard footprint | 5 × 7 mm 6-pad layout matches legacy XO footprints-enables drop-in replacement in existing designs |
Applications
| SONET/SDH Line Cards | xDSL Central Office Equipment |
|---|---|
Use Scenario: Timing reference for OC-48/OC-192 framer and mapper ICs in metro aggregation nodes. IC Role / Device Role / Timing Role: Primary low-jitter clock source providing synchronous 125 MHz and 156.25 MHz rates for payload mapping and overhead processing. Use Value: 0.37 ps RMS jitter ensures bit error rate <1e−12 under EMI stress, meeting GR-1244-CORE requirements. | Use Scenario: Dual-rate clock generation for ADSL2+/VDSL2 line cards supporting both legacy and high-speed profiles. IC Role / Device Role / Timing Role: Switchable VCXO delivering 125 MHz for baseband processing and 156.25 MHz for DAC/ADC sampling clocks. Use Value: ±50 ppm stability over –40 to +85 °C eliminates need for temperature compensation circuitry in uncontrolled CO environments. |
| 10 GbE Optical Transceivers | Clock and Data Recovery (CDR) |
Use Scenario: Reference clock for SFP+ and XFP modules operating at 10.3125 Gbps line rate. IC Role / Device Role / Timing Role: LVPECL-output VCXO supplying clean 156.25 MHz clock to CDR PLLs and serializer/deserializer cores. Use Value: DSPLL® architecture rejects power supply noise from adjacent laser drivers, maintaining <0.4 ps jitter margin. | Use Scenario: Adaptive clock recovery in retimers and repeaters where input clock stability varies across link conditions. IC Role / Device Role / Timing Role: Tunable reference enabling loop bandwidth adjustment via VC pin while maintaining dual-frequency flexibility. Use Value: 90 ppm/V KV slope provides sufficient APR for ±100 ppm input wander tracking without degrading jitter performance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-frequency VCXO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si552AD000108DGR | Same Si552 family, 644.53 MHz / 693.48 MHz dual frequencies, identical 3.3 V LVPECL output and 90 ppm/V KV | Targets higher-speed SerDes (e.g., 25G Ethernet) requiring >600 MHz references | Select when system requires >500 MHz dual-frequency capability; same footprint and control interface |
| Si53204-A01774-GM | Multi-output clock generator (not VCXO); no analog VC input; supports I²C programmability and jitter cleaning | Used where flexible frequency synthesis and jitter attenuation are needed-not for direct VCXO replacement | Choose only if design requires programmable outputs or sub-100 fs jitter; not a pin-compatible alternative |
Compared with Si552AD000108DGR, 552AD000736DG offers lower-frequency dual outputs optimized for 10G/1G Ethernet PHY layers rather than high-speed SerDes, while retaining identical DSPLL® jitter performance and thermal stability. Unlike Si53204-A01774-GM, it provides true analog voltage tuning and simpler hardware-only frequency switching.
Availability
552AD000736DG is available at Aetrix Electronics and suitable for SONET/SDH line cards, xDSL central office equipment, and 10 GbE optical transceivers requiring stable component supply, long-lifecycle support, and guaranteed RoHS-compliant sourcing.
Supply support for 552AD000736DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications infrastructure, automotive, and industrial markets.
The Si552 product line was designed specifically for high-reliability, low-jitter dual-frequency clock generation in telecom and datacom systems where traditional SAW VCXOs fail to meet phase noise and stability requirements.
FAQ
What are the exact dual output frequencies programmed in 552AD000736DG?
The 552AD000736DG is factory-programmed with two precise output frequencies: 125.000000 MHz when the FS pin is logic low (0), and 156.250000 MHz when FS is logic high (1). These values are confirmed in Skyworks' official ordering documentation for the six-digit frequency code "000736", and are traceable to the device's internal DSPLL® configuration.
Does 552AD000736DG support CMOS output format?
No, 552AD000736DG does not support CMOS output. Per Skyworks' part number convention, the "A" in position 4 of 552AD000736DG denotes 3.3 V LVPECL output. CMOS variants use codes "C" (3.3 V), "G" (2.5 V), or "J" (1.8 V), and are limited to ≤160 MHz-making them unsuitable for this specific dual-frequency configuration.
What is the Absolute Pull Range (APR) of 552AD000736DG, and how is it calculated?
The 552AD000736DG has a minimum Absolute Pull Range of ±100 ppm. This is derived from its 90 ppm/V tuning slope and 3.3 V supply: nominal pull range = 0.5 × 3.3 V × 90 ppm/V = ±148.5 ppm, then subtracting ±50 ppm temperature stability and ±10 ppm 15-year aging yields ±100 ppm APR-matching Skyworks' published specification for Option Code "D".
Can the FS pin of 552AD000736DG be left floating, or does it require a defined logic level?
The FS pin of 552AD000736DG must not be left floating. It includes an internal 17 kΩ pull-up resistor to VDD, so an unconnected FS defaults to logic high (156.25 MHz output). To select 125 MHz, FS must be actively driven low (≤0.5 V). For robust operation in noisy environments, a series resistor (e.g., 100 Ω) is recommended to limit transient current.
Is 552AD000736DG qualified for extended temperature operation beyond –40 to +85 °C?
No, 552AD000736DG is rated only for –40 to +85 °C ambient operation, as indicated by the "G" suffix in its part number. Skyworks does not offer extended-temperature variants of the Si552 family; devices intended for >85 °C operation require alternative timing solutions such as oven-controlled oscillators (OCXOs) or specialized high-temp VCXOs.
552AD000736DG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si552
- Package/Case:
- 6-SMD, No Lead
- Packaging:
- Strip
- Product Status:
- Active
- Base Resonator:
- Crystal
- Type:
- VCXO
- Frequency - Output 1:
- 644.53125MHz
- Frequency - Output 2:
- 698.812335MHz
- Frequency - Output 3:
- -
- Frequency - Output 4:
- -
- Function:
- Enable/Disable
- Output:
- LVPECL
- Voltage - Supply:
- 3.3V
- Frequency Stability:
- ±50ppm
- Operating Temperature:
- -40°C ~ 85°C
- Current - Supply (Max):
- 130mA
- Ratings:
- -
- Size / Dimension:
- 0.276" L x 0.197" W (7.00mm x 5.00mm)
- Height:
- 0.071" (1.80mm)
- Supplier Device Package:
- -
552AD000736DG FAQ
1.How can I place an order for 552AD000736DG through Aetrix?
Please submit a Request for Quotation (RFQ) for 552AD000736DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 552AD000736DG reliable?
The price and inventory of 552AD000736DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 552AD000736DG is usually 5 days.
3.What payment methods are accepted for 552AD000736DG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 552AD000736DG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 552AD000736DG?
552AD000736DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 552AD000736DG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 552AD000736DG?
For technical support, including 552AD000736DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 552AD000736DG requirements.
6.How does Aetrix verify that 552AD000736DG is sourced from the original manufacturer or authorized distributors?
All 552AD000736DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 552AD000736DG meets industry standards.
7.What is the process for return or replacement of 552AD000736DG?
All 552AD000736DG units undergo pre-shipment inspection (PSI). If there is an issue with 552AD000736DG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 552AD000736DG part is unused and in its original packaging.
Return procedure for 552AD000736DG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
552AD000736DG Tags

-
ASEMDHC-L-R
Abracon LLC

-
513FCA000270AAG
Skyworks Solutions Inc.

-
LMK61PD0A2-SIAT
Texas Instruments
-
ASEMDLV-LR
Abracon LLC
-
AMPDAFI-A09T
Abracon LLC
-
AMPDEFH-A04T
Abracon LLC
-
534DC000596DG
Skyworks Solutions Inc.
-
ASEMCLV
Abracon LLC

-
DSC6021CI2A-009TT
Microchip Technology

-
DSC6021CI2A-009UT
Microchip Technology

-
DSC6021CI2A-009WT
Microchip Technology

-
DSC6021CI2A-009YT
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
