Skyworks Solutions Inc. 552BA000964DGR

Overview

552BA000964DGR from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed frequencies of 125 MHz and 156.25 MHz, 3.3 V LVDS output, ±50 ppm temperature stability, and 90 ppm/V tuning slope. It delivers ultra-low phase jitter (0.37 ps RMS, 12 kHz–20 MHz) and operates across –40 to +85 °C in an industry-standard 5 × 7 mm 6-pin surface-mount package. It serves as a low-noise clock source in 10 GbE LAN/WAN and optical module timing paths.

For engineers reviewing the 552BA000964DGR datasheet, 552BA000964DGR pinout, 552BA000964DGR application, or 552BA000964DGR equivalent, this page provides verified electrical specs, dual-frequency behavior, DSPLL®-based supply noise rejection, LVDS output drive capability, and real-world settling time (≤10 ms after FS toggle) - all confirmed for this exact part number per Skyworks document 207110A (Rev D, March 2025).

Technical Context

The 552BA000964DGR implements Skyworks' 3rd-generation DSPLL® architecture with a fixed internal crystal reference, enabling two user-selectable output frequencies (125 MHz and 156.25 MHz) via the digital Frequency Select (FS) input. Its analog VC pin accepts 0–VDD control voltage with 90 ppm/V tuning slope, supporting precise PLL loop calibration.

It integrates LVDS differential outputs with 0.7 VPP typical swing, 45–55% duty cycle symmetry, and 350 ps max rise/fall time. The device achieves 0.37 ps RMS phase jitter (12 kHz–20 MHz) at 125–500 MHz range with KV = 90 ppm/V, and supports tristate mode with ≤75 mA quiescent current.

Key Specifications

Pinout & Package

552BA000964DGR uses an industry-standard 5 × 7 mm, 6-pad surface-mount package (RoHS-compliant, Pb-free), with exposed pad not electrically connected. Pin 1 is marked by a dot; top view orientation matches Skyworks Figure 2 (Rev D).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Compared with 552BA000964DGR, Si552BA000108DGR offers higher-frequency dual outputs but requires LVPECL termination and delivers higher jitter (0.50 ps) at its operating range, while Si53204-A01774-GM provides four outputs and digital programmability but eliminates analog VC tuning and hardware-based FS switching - making it unsuitable for real-time analog PLL calibration.

Availability

552BA000964DGR is available at Aetrix Electronics and suitable for 10 GbE LAN/WAN infrastructure, optical transport modules, and SONET/SDH systems requiring stable component supply, dual-rate timing agility, and guaranteed long-term frequency stability.

Supply support for 552BA000964DGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, and industrial markets.

The Si552 product line delivers dual-frequency, DSPLL®-based VCXOs designed specifically for high-speed communication systems demanding ultra-low jitter, field-programmable tuning, and long-term frequency stability without oven control.

FAQ

What are the exact factory-programmed frequencies for 552BA000964DGR?

The 552BA000964DGR is configured with two precise output frequencies: 125.000000 MHz when FS = 0, and 156.250000 MHz when FS = 1. These values are permanently programmed into the device at Skyworks' factory and cannot be altered in the field. Both frequencies are specified in Table 3 of Skyworks document 207110A (Rev D), and their accuracy is maintained within ±50 ppm over –40 to +85 °C.

Does 552BA000964DGR support tristate mode, and how is it enabled?

Yes, 552BA000964DGR supports tristate mode to disable CLK+/CLK− outputs. Tristate is activated by driving the FS pin low (0 V) while simultaneously applying 0 V to the VC pin - this dual-condition entry is defined in Skyworks' functional description and electrical specifications. In tristate, supply current drops to ≤75 mA, and outputs present high impedance, allowing safe bus sharing in multi-oscillator systems.

What is the maximum allowable control voltage range on the VC pin of 552BA000964DGR?

The VC pin of 552BA000964DGR accepts a control voltage from 0 V to VDD (3.3 V), as specified in Table 2 of Skyworks document 207110A. Operation outside this range - including negative voltages or voltages exceeding VDD + 0.3 V - violates Absolute Maximum Ratings and may cause permanent damage. The nominal tuning point (fO) occurs at VC = VDD/2 = 1.65 V, and linear tuning is guaranteed between 10–90% of VDD (0.33–2.97 V).

How does the 90 ppm/V tuning slope of 552BA000964DGR impact PLL loop design?

The 90 ppm/V KV value of 552BA000964DGR defines the frequency deviation per volt applied to VC. With VDD = 3.3 V, this yields a nominal APR of ±148.5 ppm (0.5 × 3.3 × 90), reduced to ±80 ppm minimum after subtracting ±50 ppm stability and ±10 ppm aging. This slope enables robust loop filter design with moderate gain while minimizing sensitivity to control-line noise - a key advantage over higher-KV SAW VCXOs that require tighter filtering to maintain jitter performance.

Is the 5 × 7 mm package of 552BA000964DGR compatible with standard PCB land patterns for 6-pin oscillators?

Yes, 552BA000964DGR uses the industry-standard 5 × 7 mm, 6-pad footprint defined in Skyworks Figure 3 (Rev D). Pad dimensions (e.g., GD = 0.84 mm, GE = 2.00 mm) and pitch (2.54 mm) comply with IPC-7351 guidelines. The land pattern requires no custom layout - standard 5 × 7 mm oscillator footprints used for Si5xx, ECS, and TXC devices are mechanically and solder-reflow compatible with 552BA000964DGR.