Skyworks Solutions Inc. 552CD000260DGR

Overview

552CD000260DGR from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed output frequencies of 156.25 MHz and 125.00 MHz, 3.3 V CMOS output, ±50 ppm temperature stability, and 90 ppm/V tuning slope. It delivers low-jitter clock generation in telecom and networking systems requiring precise frequency agility between two fixed rates.

For engineers reviewing the 552CD000260DGR datasheet, 552CD000260DGR pinout, 552CD000260DGR application, or 552CD000260DGR equivalent, this page provides verified electrical specs, dual-frequency switching behavior, CMOS drive capability up to 160 MHz, thermal derating guidance, and validated alternatives for SONET/SDH and 10GbE timing subsystems.

Technical Context

The 552CD000260DGR implements Skyworks' third-generation DSPLL® architecture with an internal fixed-crystal reference and digital synthesis to generate two user-defined frequencies (156.25 MHz and 125.00 MHz) selectable via the FS pin. Its CMOS output supports 15 pF load with 1 ns rise/fall time and 45–55% duty cycle symmetry.

It operates across –40 °C to +85 °C with 3.3 V supply, draws 90–98 mA typical current, and achieves 0.63–0.67 ps RMS phase jitter (12 kHz–20 MHz) at 125–156 MHz using 90 ppm/V KV tuning. The VC input exhibits 500 kΩ impedance and accepts 0–VDD control voltage with nominal VCNOM = VDD/2.

Key Specifications

Pinout & Package

552CD000260DGR uses an industry-standard 5 mm × 7 mm, 6-pad surface-mount package (RoHS-compliant, Pb-free). Pin 1 is marked by a dot on the top surface.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Compared with Si552AC000260DGR and Si552BD000260DGR, the 552CD000260DGR uniquely balances 3.3 V CMOS compatibility, 156.25/125.00 MHz dual-rate precision, and sub-0.7 ps jitter-making it optimal for cost-sensitive, space-constrained telecom PHY designs without differential routing overhead.

Availability

552CD000260DGR is available at Aetrix Electronics and suitable for SONET/SDH line cards, 10GbE LAN/WAN PHYs, and xDSL central office equipment requiring stable component supply across extended product lifecycles.

Supply support for 552CD000260DGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, and infrastructure markets.

The Si552 product line delivers programmable dual-frequency VCXOs for telecom and networking systems where deterministic clock agility, low jitter, and long-term stability are critical-enabling simplified timing architectures in high-reliability infrastructure.

FAQ

What are the exact factory-programmed frequencies for 552CD000260DGR?

The 552CD000260DGR is configured with two precise output frequencies: 156.25 MHz when the FS pin is logic low (0), and 125.00 MHz when FS is logic high (1). These values correspond to the six-digit frequency code "000260" in the part number and are permanently programmed during manufacturing-no field reconfiguration is possible. Both frequencies meet ±50 ppm stability over –40 °C to +85 °C.

Does 552CD000260DGR support tristate functionality?

No, the 552CD000260DGR does not include an output enable (OE) pin or tristate capability. Its CMOS output remains active whenever VDD is applied and VC is within valid range. For power-gated operation, system-level control must be implemented externally-such as disabling VDD via a load switch-or selecting a variant like 552CD000260DGR with OE option (if available in ordering matrix).

What is the maximum allowable control voltage (VC) range for 552CD000260DGR?

The VC pin on the 552CD000260DGR accepts 0 V to VDD (3.3 V) continuously. Operation outside this range-specifically below –0.5 V or above 3.63 V-violates Absolute Maximum Ratings and may cause permanent damage. The nominal tuning point is VCNOM = VDD/2 = 1.65 V, where output frequency equals the center of the ±80 ppm APR window.

How does the 90 ppm/V tuning slope affect phase jitter performance in 552CD000260DGR?

At 90 ppm/V KV, the 552CD000260DGR achieves 0.67 ps RMS phase jitter (12 kHz–20 MHz) at 125 MHz-optimized per AN266 guidance to balance APR requirement and noise immunity. Higher KV options (e.g., 135 ppm/V) increase jitter to 0.74 ps, while lower KV (45 ppm/V) reduces jitter to 0.63 ps but narrows APR to ±30 ppm. The 90 ppm/V setting was selected to meet ±80 ppm APR while maintaining OC-48 compliance.

Is the 552CD000260DGR compliant with lead-free and RoHS requirements?

Yes, the 552CD000260DGR is Pb-free and RoHS-compliant, as confirmed by Skyworks' MSL 1 moisture sensitivity rating and JEDEC J-STD-020C soldering profile (260 °C peak, 20–40 sec). The top marking includes a "+" symbol indicating RoHS compliance, and the device meets MIL-STD-883F qualification for mechanical shock, vibration, and thermal cycling.