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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 552CG000199DG

Name: 552CG000199DG
Brand: Skyworks Solutions Inc.
SKU: 552CG000199DG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 552CG000199DG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 552CG000199DG.pdf

Description:: XTAL OSC VCXO 3.3V 6SMD

Quantity:: RFQ Add To RFQ list

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Inventory:3,290

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Product details

Overview

552CG000199DG from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed frequencies of 100 MHz and 125 MHz, 3.3 V CMOS output, ±50 ppm temperature stability, 90 ppm/V tuning slope, and operation from –40 to +85 °C in a 5 × 7 mm surface-mount package. It delivers low-jitter clocking for telecom timing recovery and optical module synchronization.

For engineers reviewing the 552CG000199DG datasheet, 552CG000199DG pinout, 552CG000199DG application, or 552CG000199DG equivalent, this page provides verified electrical specs, dual-frequency switching behavior, VC control voltage linearity, FS-selectable output mode, and real-world jitter performance across OC-48/OC-192 integration bands.

Technical Context

The 552CG000199DG implements Skyworks' third-generation DSPLL® architecture to synthesize two precise output frequencies from a single internal fixed-crystal reference, enabling frequency agility without crystal swaps. Its analog VC input accepts 0–VDD control voltage with 90 ppm/V tuning slope and ±50 ppm total stability over temperature and aging.

Frequency selection is performed via the digital FS pin, which toggles between the two preprogrammed frequencies (100 MHz and 125 MHz) with <10 ms settling time. The CMOS output drives 15 pF loads with 1 ns rise/fall time, 45–55% duty cycle symmetry, and RMS phase jitter as low as 0.63 ps (12 kHz–20 MHz) at 100 MHz.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	100 MHz (FS = 0) and 125 MHz (FS = 1); enables dual-rate clock domain bridging in serial data links
Output Format	CMOS; compatible with standard logic interfaces, supports 32 mA drive into 15 pF load
Supply Voltage	3.3 V ±10%; supports industrial-grade power rail tolerance without external regulation
Tuning Slope (KV)	90 ppm/V; balances APR margin (±80 ppm min) and jitter sensitivity for PLL loop stability
Temp Stability	±50 ppm over –40 to +85 °C; meets SONET/SDH GR-1244-CORE Class 3 requirements
Phase Jitter (RMS)	0.63 ps (12 kHz–20 MHz); ensures <0.1 UI jitter budget for 10 GbE NRZ signaling
Aging (15 yr)	±10 ppm; eliminates need for field recalibration in deployed optical transport systems

Pinout & Package

552CG000199DG is housed in an industry-standard, RoHS-compliant, 6-pad 5 × 7 mm surface-mount package (MSL 1, Pb-free). Pin 1 is marked by a dot on the top surface.

Pin/Terminal	Circuit Role	Design Meaning
1 - VC	Analog control input	Accepts 0–3.3 V tuning voltage; 500 kΩ input impedance; nominal center at 1.65 V for f_O
2 - FS	Digital frequency select	Active-high logic selects 100 MHz (FS = 0) or 125 MHz (FS = 1); internal 17 kΩ pull-up to VDD
3 - GND	Ground reference	Common return for power, output, and control paths; requires low-inductance PCB connection
4 - CLK+	CMOS clock output	Single-ended 3.3 V CMOS signal; VOH ≥ 2.64 V, VOL ≤ 0.4 V @ 32 mA; 1 ns edge rate
5 - CLK−	No-connect (NC)	Not bonded for CMOS output configuration; must be left floating or grounded per layout guidelines
6 - VDD	Power supply	3.3 V main supply; decoupling capacitor (0.1 µF + 10 µF) required within 5 mm of pin

Key Features

Feature	Design Value
Dual-frequency programmability	Two factory-set frequencies (100/125 MHz) selected via single-pin FS control-no reprogramming or firmware needed
DSPLL® jitter suppression	0.63 ps RMS phase jitter (12 kHz–20 MHz) enables OC-48/OC-192 CDR compliance without external cleanup PLL
Fixed internal crystal reference	Eliminates SAW resonator drift; achieves ±10 ppm 15-year aging vs. ±30 ppm typical for SAW-based VCXOs
Supply noise rejection	Superior PSR from DSPLL architecture allows direct use in noisy switch-mode power supply domains (e.g., line cards)
Industry-standard footprint	5 × 7 mm 6-pad land pattern matches legacy XO footprints-enables drop-in replacement without PCB redesign

Applications

SONET/SDH Line Cards	xDSL Central Office Equipment
Use Scenario: Timing recovery and frame alignment in OC-48/OC-192 framer ASICs requiring dual-reference clocks for upstream/downstream channel bonding. IC Role / Device Role / Timing Role: Dual-frequency VCXO providing master clock and retiming reference with sub-UI jitter for SERDES lock acquisition. Use Value: 0.63 ps RMS jitter and ±50 ppm stability ensure BER <1e−12 under temperature cycling and supply ripple.	Use Scenario: Synchronized clock generation for multi-port DSLAM line cards supporting ADSL2+/VDSL2 vectoring with dynamic profile switching. IC Role / Device Role / Timing Role: Frequency-agile timing source enabling seamless transition between 13.5 MHz (ADSL) and 17.664 MHz (VDSL) line rates. Use Value: FS pin toggling in <10 ms allows real-time rate adaptation without clock interruption or PLL relock delay.
10 GbE Optical Transceivers	Clock and Data Recovery (CDR) Modules
Use Scenario: Low-jitter clock synthesis for 10GBASE-LR/LW PHYs in SFP+ modules operating in temperature-varying chassis environments. IC Role / Device Role / Timing Role: Primary clock generator delivering 156.25 MHz reference to gearbox and serializer ICs. Use Value: ±50 ppm stability over –40 to +85 °C avoids thermal derating and maintains link margin across full industrial range.	Use Scenario: Reference clock provisioning for high-speed CDR ICs in OTN muxponders where dual-rate operation supports multiple client interfaces (e.g., STM-64 + 10GbE). IC Role / Device Role / Timing Role: Dual-output VCXO supplying independent 125 MHz (Ethernet) and 155.52 MHz (SONET) references from one device. Use Value: Single-device dual-frequency capability reduces BOM count, board area, and power vs. two discrete XO solutions.

SONET/SDH Line Cards

xDSL Central Office Equipment

Use Scenario: Timing recovery and frame alignment in OC-48/OC-192 framer ASICs requiring dual-reference clocks for upstream/downstream channel bonding.

IC Role / Device Role / Timing Role: Dual-frequency VCXO providing master clock and retiming reference with sub-UI jitter for SERDES lock acquisition.

Use Value: 0.63 ps RMS jitter and ±50 ppm stability ensure BER <1e−12 under temperature cycling and supply ripple.

Use Scenario: Synchronized clock generation for multi-port DSLAM line cards supporting ADSL2+/VDSL2 vectoring with dynamic profile switching.

IC Role / Device Role / Timing Role: Frequency-agile timing source enabling seamless transition between 13.5 MHz (ADSL) and 17.664 MHz (VDSL) line rates.

Use Value: FS pin toggling in <10 ms allows real-time rate adaptation without clock interruption or PLL relock delay.

10 GbE Optical Transceivers

Clock and Data Recovery (CDR) Modules

Use Scenario: Low-jitter clock synthesis for 10GBASE-LR/LW PHYs in SFP+ modules operating in temperature-varying chassis environments.

IC Role / Device Role / Timing Role: Primary clock generator delivering 156.25 MHz reference to gearbox and serializer ICs.

Use Value: ±50 ppm stability over –40 to +85 °C avoids thermal derating and maintains link margin across full industrial range.

Use Scenario: Reference clock provisioning for high-speed CDR ICs in OTN muxponders where dual-rate operation supports multiple client interfaces (e.g., STM-64 + 10GbE).

IC Role / Device Role / Timing Role: Dual-output VCXO supplying independent 125 MHz (Ethernet) and 155.52 MHz (SONET) references from one device.

Use Value: Single-device dual-frequency capability reduces BOM count, board area, and power vs. two discrete XO solutions.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si550AC000108DG	Single-frequency Si550 variant; same 3.3 V CMOS output, ±50 ppm stability, but lacks FS-selectable second frequency	Only suitable where fixed 100 MHz clock suffices; no runtime frequency agility	Select only if dual-frequency switching is unnecessary and cost reduction is prioritized over flexibility
MAX2623EUA+	Voltage-controlled SAW oscillator; 10–150 MHz range, ±100 ppm stability, higher 1.2 ps jitter, no dual-frequency capability	Limited to lower-frequency applications; unsuitable for OC-192 or 10 GbE due to jitter and stability limits	Consider only for legacy designs requiring SAW-based form factor compatibility and relaxed jitter specs

Compared with 552CG000199DG, the Si550AC000108DG saves cost but removes frequency agility, while the MAX2623EUA+ offers broader tuning range yet fails to meet OC-192 jitter or dual-rate requirements-making 552CG000199DG the sole option satisfying telecom-grade dual-frequency, low-jitter, and industrial-temperature needs.

Availability

552CG000199DG is available at Aetrix Electronics and suitable for SONET/SDH line cards, xDSL central office equipment, and 10 GbE optical transceivers requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.

Supply support for 552CG000199DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog semiconductors, specializing in RF, timing, and precision analog components for communications infrastructure and high-reliability systems.

The Si552 product line was designed specifically for dual-frequency, low-jitter clock generation in telecom and datacom equipment where traditional VCXOs lack frequency agility or jitter performance.

FAQ

What are the two factory-programmed output frequencies of the 552CG000199DG?

The 552CG000199DG is configured with 100 MHz as the first frequency (FS = 0) and 125 MHz as the second frequency (FS = 1). These values are permanently programmed during manufacturing and cannot be altered in the field. Both frequencies operate with identical CMOS output characteristics, supply voltage, and temperature stability specifications as defined in the official Skyworks datasheet revision D.

Does the 552CG000199DG support LVDS or LVPECL outputs?

No, the 552CG000199DG does not support LVDS or LVPECL outputs. Its part number suffix "C" explicitly denotes CMOS output format per Skyworks' ordering convention. The device delivers single-ended 3.3 V CMOS signals compliant with standard logic thresholds and 15 pF load drive capability. For LVDS or LVPECL variants, engineers must select different part numbers such as 552AB000199DG (LVDS) or 552AA000199DG (LVPECL).

What is the absolute pull range (APR) of the 552CG000199DG at 3.3 V supply?

The 552CG000199DG has a minimum absolute pull range (APR) of ±80 ppm at 3.3 V supply, derived from its 90 ppm/V tuning slope and ±50 ppm temperature stability specification. This value accounts for worst-case stability, aging (±10 ppm), and tuning linearity deviation, ensuring reliable lock range for PLL applications across full industrial temperature and lifetime conditions.

How does the FS pin function on the 552CG000199DG?

The FS pin on the 552CG000199DG is a digital input that selects between its two factory-programmed frequencies: logic low (FS = 0) selects 100 MHz, and logic high (FS = 1) selects 125 MHz. It features an internal 17 kΩ pull-up resistor to VDD, so an external pull-down is required for FS = 0 operation. Frequency switching settles within 10 ms, enabling dynamic rate adaptation in protocol-aware systems.

Is the 552CG000199DG pin-compatible with other Si552 variants?

Yes, all Si552 devices-including the 552CG000199DG-share identical 6-pin 5 × 7 mm package dimensions, pinout assignment, and land pattern requirements per Skyworks' package outline documentation. This uniformity allows mechanical and layout compatibility across output formats (CMOS/LVDS/LVPECL/CML), supply voltages (1.8/2.5/3.3 V), and tuning slopes-enabling design reuse and simplified inventory management.

552CG000199DG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si552

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: VCXO

Frequency - Output 1:: 11.2896MHz, 12.288MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 98mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

552CG000199DG FAQ

1.How can I place an order for 552CG000199DG through Aetrix?

Please submit a Request for Quotation (RFQ) for 552CG000199DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 552CG000199DG reliable?

The price and inventory of 552CG000199DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 552CG000199DG is usually 5 days.

3.What payment methods are accepted for 552CG000199DG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 552CG000199DG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 552CG000199DG?

552CG000199DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 552CG000199DG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 552CG000199DG?

For technical support, including 552CG000199DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 552CG000199DG requirements.

6.How does Aetrix verify that 552CG000199DG is sourced from the original manufacturer or authorized distributors?

All 552CG000199DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 552CG000199DG meets industry standards.

7.What is the process for return or replacement of 552CG000199DG?

All 552CG000199DG units undergo pre-shipment inspection (PSI). If there is an issue with 552CG000199DG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 552CG000199DG part is unused and in its original packaging.

Return procedure for 552CG000199DG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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