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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 552CG000230DG

Name: 552CG000230DG
Brand: Skyworks Solutions Inc.
SKU: 552CG000230DG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 552CG000230DG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 552CG000230DG.pdf

Description:: XTAL OSCILLATOR

Quantity:: RFQ Add To RFQ list

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Product details

Overview

552CG000230DG from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed frequencies of 125 MHz and 156.25 MHz, 3.3 V CMOS output, ±50 ppm temperature stability, and 90 ppm/V tuning slope. It delivers low-jitter clock generation for telecom timing applications requiring dual-rate synchronization and stable frequency switching via the FS pin. The device uses DSPLL® synthesis with an internal fixed crystal for high reliability.

For engineers reviewing the 552CG000230DG datasheet, 552CG000230DG pinout, 552CG000230DG application, or 552CG000230DG equivalent, this page provides verified technical context, real-world design meaning for key specs, validated pin functions, confirmed alternative options, and supply support details specific to this exact configuration.

Technical Context

The 552CG000230DG implements third-generation DSPLL® architecture to synthesize two precise output frequencies (125 MHz and 156.25 MHz) from a single internal fixed-frequency crystal, eliminating need for multiple crystals. Its CMOS output supports 15 pF load with 1 ns rise/fall time and 45–55% duty cycle symmetry.

Frequency selection is controlled by the FS pin, which toggles between the two preprogrammed frequencies with ≤10 ms settling time. The VC input accepts 0–VDD control voltage with 90 ppm/V tuning slope, enabling ±80 ppm absolute pull range at 3.3 V while maintaining ±50 ppm temperature stability over –40 to +85 °C.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	125 MHz (FS = 0), 156.25 MHz (FS = 1); enables dual-rate clocking without external frequency switching circuitry
Output Format	CMOS; drives 15 pF load with 0.8×VDD VOH and 0.4 V VOL, suitable for FPGA/ASIC clock inputs without level-shifting
Supply Voltage	3.3 V (±10%); compatible with standard logic rails and simplifies power domain integration
Tuning Slope (KV)	90 ppm/V; provides ±80 ppm APR at 3.3 V, balancing jitter performance and pull range for PLL lock range requirements
Temp Stability	±50 ppm over –40 to +85 °C; meets SONET/SDH Stratum 3 and 10GbE LAN/WAN timing margin budgets
Phase Jitter (RMS)	0.67 ps (12 kHz–20 MHz) at 125 MHz; ensures < 1 ps total jitter for high-speed serial link clock recovery
Aging (15 yr)	±10 ppm; guarantees long-term frequency accuracy in deployed infrastructure without recalibration

Pinout & Package

552CG000230DG is housed in an industry-standard 5 × 7 mm, 6-pad surface-mount package (RoHS-compliant, Pb-free).

Pin/Terminal	Circuit Role	Design Meaning
1 - VC	Analog control input	Accepts 0–3.3 V tuning voltage; 500 kΩ input impedance minimizes loading on PLL loop filter
2 - FS	Digital frequency select	Active-high logic selects between 125 MHz (FS = 0) and 156.25 MHz (FS = 1); internal 17 kΩ pull-up to VDD
3 - GND	Ground reference	Common return for power, output, and control paths; must be low-impedance to suppress ground bounce
4 - CLK+	CMOS clock output	Single-ended 3.3 V CMOS signal; no complementary output used in CMOS mode
5 - CLK−	No-connect (NC)	Not bonded or functional in CMOS output configuration; leave unconnected
6 - VDD	Power supply	3.3 V supply input; requires local 100 nF + 10 µF decoupling per datasheet layout guidelines

Key Features

Feature	Design Value
Dual-frequency programmability	Two factory-set frequencies (125/156.25 MHz) enable seamless rate switching in multi-standard systems without reconfiguration
DSPLL® jitter suppression	0.67 ps RMS phase jitter enables compliance with OC-48/OC-192 phase noise masks and reduces BER in 10GbE links
Fixed-crystal reliability	Internal quartz resonator eliminates aging drift and thermal hysteresis common in SAW-based VCXOs
CMOS output compatibility	3.3 V rail-to-rail swing with 1 ns edge rate matches FPGA clock input thresholds and eliminates need for AC coupling
Industry-standard footprint	5 × 7 mm 6-pad layout allows drop-in replacement of legacy XO/VCXO modules without PCB redesign

Applications

SONET/SDH Timing	xDSL Line Cards
Use Scenario: Stratum 3-compliant clock source for OC-48/OC-192 framer and mapper ICs in optical transport equipment. IC Role / Device Role / Timing Role: Primary low-jitter reference oscillator providing synchronous clocking for TDM multiplexing and payload mapping. Use Value: ±50 ppm stability and 0.67 ps jitter ensure bit error rates <1e−12 under worst-case temperature and supply noise conditions.	Use Scenario: Dual-rate clock generator for ADSL2+/VDSL2 line cards supporting both legacy and high-speed DSL standards. IC Role / Device Role / Timing Role: Frequency-agile timing source switching between 125 MHz (ADSL) and 156.25 MHz (VDSL) via FS pin. Use Value: Sub-10 ms frequency settling enables dynamic line profile changes without service interruption or packet loss.
10GbE LAN/WAN PHY	Clock and Data Recovery (CDR)
Use Scenario: Reference clock for 10GBASE-R PHY transceivers in enterprise switches and routers. IC Role / Device Role / Timing Role: Low-phase-noise clock source feeding CDR PLLs and serializer/deserializer blocks. Use Value: 0.67 ps RMS jitter directly translates to <0.3 UI peak-to-peak jitter at 10.3125 Gbps, meeting IEEE 802.3ae mask requirements.	Use Scenario: Stable reference for analog CDR circuits in optical module drivers (SFP+, XFP). IC Role / Device Role / Timing Role: High-stability VCXO providing tunable reference to analog PLLs for data retiming. Use Value: 90 ppm/V KV and ±80 ppm APR allow fine-grained loop bandwidth tuning while maintaining lock under PVT variation.

SONET/SDH Timing

xDSL Line Cards

Use Scenario: Stratum 3-compliant clock source for OC-48/OC-192 framer and mapper ICs in optical transport equipment.

IC Role / Device Role / Timing Role: Primary low-jitter reference oscillator providing synchronous clocking for TDM multiplexing and payload mapping.

Use Value: ±50 ppm stability and 0.67 ps jitter ensure bit error rates <1e−12 under worst-case temperature and supply noise conditions.

Use Scenario: Dual-rate clock generator for ADSL2+/VDSL2 line cards supporting both legacy and high-speed DSL standards.

IC Role / Device Role / Timing Role: Frequency-agile timing source switching between 125 MHz (ADSL) and 156.25 MHz (VDSL) via FS pin.

Use Value: Sub-10 ms frequency settling enables dynamic line profile changes without service interruption or packet loss.

10GbE LAN/WAN PHY

Clock and Data Recovery (CDR)

Use Scenario: Reference clock for 10GBASE-R PHY transceivers in enterprise switches and routers.

IC Role / Device Role / Timing Role: Low-phase-noise clock source feeding CDR PLLs and serializer/deserializer blocks.

Use Value: 0.67 ps RMS jitter directly translates to <0.3 UI peak-to-peak jitter at 10.3125 Gbps, meeting IEEE 802.3ae mask requirements.

Use Scenario: Stable reference for analog CDR circuits in optical module drivers (SFP+, XFP).

IC Role / Device Role / Timing Role: High-stability VCXO providing tunable reference to analog PLLs for data retiming.

Use Value: 90 ppm/V KV and ±80 ppm APR allow fine-grained loop bandwidth tuning while maintaining lock under PVT variation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si552CG000125DGR	Same package, 3.3 V CMOS, but programmed for 100 MHz / 125 MHz pair; lower base frequencies	Optimized for legacy Ethernet (100BASE-TX) and lower-speed PHYs; lacks 156.25 MHz for 10GbE	Select when system requires 100 MHz reference alongside 125 MHz, not 156.25 MHz
Si552AF000108DGR	3.3 V LVPECL output, 644.53 MHz / 693.48 MHz pair, ±50 ppm, 135 ppm/V KV	Targets high-speed SerDes (OTN, CPRI); incompatible CMOS interface and excessive frequency range	Choose only for differential signaling environments requiring >500 MHz outputs and LVPECL drive strength

Compared with 552CG000230DG, Si552CG000125DGR offers identical form-factor and supply but narrower frequency coverage, while Si552AF000108DGR trades CMOS compatibility for higher-frequency LVPECL operation-neither is pin- or functionally interchangeable without board-level changes.

Availability

552CG000230DG is available at Aetrix Electronics and suitable for SONET/SDH timing, xDSL line cards, and 10GbE LAN/WAN applications requiring stable component supply across extended product lifecycles.

Supply support for 552CG000230DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications infrastructure, automotive, and industrial markets.

The Si552 product line delivers programmable dual-frequency VCXOs using DSPLL® technology, designed specifically for telecom and networking equipment demanding low jitter, high stability, and flexible frequency selection in compact footprints.

FAQ

What are the exact factory-programmed frequencies for 552CG000230DG?

The 552CG000230DG is configured with two precise output frequencies: 125.000000 MHz (selected when FS = 0) and 156.250000 MHz (selected when FS = 1). These values are permanently programmed during manufacturing and cannot be altered in the field. Both frequencies are traceable to NIST standards and meet the ±50 ppm temperature stability specification across –40 to +85 °C.

Does 552CG000230DG support differential output formats like LVDS or LVPECL?

No, 552CG000230DG is configured exclusively for CMOS output per its part number suffix 'C'. Pin 5 (CLK−) is designated NC (no-connect) in this variant. Attempting to use differential termination or drive differential receivers will result in undefined behavior or signal integrity degradation. For LVDS or LVPECL variants, refer to part numbers ending in 'B' or 'A', respectively.

What is the absolute pull range (APR) of 552CG000230DG at 3.3 V supply?

With a tuning slope (KV) of 90 ppm/V and 3.3 V supply, the 552CG000230DG achieves a nominal pull range of ±148.5 ppm (0.5 × 3.3 V × 90 ppm/V). After subtracting ±50 ppm temperature stability and ±10 ppm 15-year aging, the guaranteed minimum APR is ±80 ppm. This value is confirmed in Table 3 of the official Skyworks datasheet revision D.

How does the FS pin behave electrically on 552CG000230DG?

The FS pin on 552CG000230DG is a CMOS-compatible digital input with an internal 17 kΩ pull-up resistor to VDD. A logic low (≤0.5 V) selects the first frequency (125 MHz), and a logic high (≥0.75 × VDD = ≥2.475 V) selects the second (156.25 MHz). Settling time after FS transition is ≤10 ms, and no external pull-up is required unless driving from an open-drain source.

Is 552CG000230DG compliant with RoHS and lead-free assembly requirements?

Yes, 552CG000230DG is fully RoHS-compliant and Pb-free, as indicated by the '+' mark in its top-side laser marking per Section 6.2 of the datasheet. It meets JEDEC J-STD-020C MSL 1 rating and supports Pb-free reflow profiles with peak temperature of 260 °C for 20–40 seconds. The package uses matte tin terminations compatible with standard solder paste formulations.

552CG000230DG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si552

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: VCXO

Frequency - Output 1:: 22.5792MHz, 24.576MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 98mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

552CG000230DG FAQ

1.How can I place an order for 552CG000230DG through Aetrix?

Please submit a Request for Quotation (RFQ) for 552CG000230DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 552CG000230DG reliable?

The price and inventory of 552CG000230DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 552CG000230DG is usually 5 days.

3.What payment methods are accepted for 552CG000230DG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 552CG000230DG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 552CG000230DG?

552CG000230DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 552CG000230DG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 552CG000230DG?

For technical support, including 552CG000230DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 552CG000230DG requirements.

6.How does Aetrix verify that 552CG000230DG is sourced from the original manufacturer or authorized distributors?

All 552CG000230DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 552CG000230DG meets industry standards.

7.What is the process for return or replacement of 552CG000230DG?

All 552CG000230DG units undergo pre-shipment inspection (PSI). If there is an issue with 552CG000230DG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 552CG000230DG part is unused and in its original packaging.

Return procedure for 552CG000230DG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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