Skyworks Solutions Inc. 552CH000118DG

Overview

552CH000118DG from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed output frequencies of 125 MHz and 156.25 MHz, 3.3 V CMOS output, ±50 ppm temperature stability, and 90 ppm/V tuning slope. It uses DSPLL® synthesis for low-jitter clock generation in telecom timing and synchronization applications.

For engineers reviewing the 552CH000118DG datasheet, 552CH000118DG pinout, 552CH000118DG application, or 552CH000118DG equivalent, this page delivers verified electrical specs, dual-frequency behavior, CMOS drive capability up to 160 MHz, thermal resistance data, and real-world jitter performance across VC tuning slopes - all critical for SONET/SDH and 10GbE clock recovery designs.

Technical Context

The 552CH000118DG implements third-generation DSPLL® circuitry with an internal fixed crystal reference, enabling two user-selectable output frequencies (125 MHz and 156.25 MHz) via the FS pin. Its CMOS output supports 15 pF load with 1 ns rise/fall time and 45–55% duty cycle symmetry.

It operates across –40 °C to +85 °C with 3.3 V supply, draws 90–98 mA typical current, and achieves 0.63–0.67 ps RMS phase jitter (12 kHz–20 MHz) at 125–156.25 MHz using 90 ppm/V KV tuning. The VC input has 500 kΩ impedance and accepts 0–VDD control voltage.

Key Specifications

Pinout & Package

552CH000118DG is housed in a RoHS-compliant, lead-free 5 mm × 7 mm surface-mount package with six terminals arranged in a single row. Pin 1 is marked by a dot on the top surface.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Compared with Si550AC000118DG and 552AH000118DG, the 552CH000118DG uniquely delivers dual-rate 3.3 V CMOS timing in a drop-in-compatible 5×7 mm footprint - enabling hardware-based frequency switching without sacrificing jitter performance or thermal robustness.

Availability

552CH000118DG is available at Aetrix Electronics and suitable for SONET/SDH line cards, xDSL central office equipment, and 10GbE LAN/WAN switches requiring stable component supply, long-lifecycle support, and guaranteed factory programming accuracy.

Supply support for 552CH000118DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for communications infrastructure, automotive, and industrial markets.

The Si552 product line was designed specifically for high-reliability, dual-frequency clock generation in telecom and networking equipment - combining DSPLL® synthesis with factory-programmable flexibility to replace multiple discrete oscillators.

FAQ

What are the exact factory-programmed frequencies for 552CH000118DG?

The 552CH000118DG is programmed with two precise output frequencies: 125.000000 MHz when the FS pin is logic low, and 156.250000 MHz when FS is logic high. These values are laser-trimmed during manufacturing and verified per Skyworks' production test flow - no field calibration is required. Both frequencies are specified at VCNOM = VDD/2 and meet ±50 ppm stability over –40 °C to +85 °C.

Does 552CH000118DG support LVPECL or LVDS outputs?

No, 552CH000118DG is configured exclusively for CMOS output, as indicated by the "C" in position 4 of the part number. It delivers rail-to-rail swing into 15 pF with VOH ≥ 0.8×VDD and VOL ≤ 0.4 V. LVPECL and LVDS variants exist in the Si552 family (e.g., 552AFxxx for LVPECL), but 552CH000118DG does not support differential signaling modes - CLK− is a no-connect terminal.

What is the absolute pull range (APR) of 552CH000118DG at 3.3 V supply?

With a 90 ppm/V tuning slope and 3.3 V supply, the 552CH000118DG achieves a nominal pull range of ±148.5 ppm (0.5 × 3.3 V × 90 ppm/V). After subtracting ±50 ppm temperature stability and ±10 ppm 15-year aging, its guaranteed minimum Absolute Pull Range (APR) is ±88.5 ppm - consistent with the "D" code in the second option field of the part number, which specifies ≥80 ppm APR for 3.3 V operation.

How does the 552CH000118DG's phase jitter compare to SAW-based VCXOs?

The 552CH000118DG achieves 0.67 ps RMS phase jitter (12 kHz–20 MHz) at 125–156.25 MHz - approximately 3× lower than typical SAW-based VCXOs operating at similar frequencies. This improvement stems from DSPLL®'s superior supply noise rejection and the fixed-crystal architecture, which eliminates SAW resonator sensitivity to temperature and aging. Measured PSR exceeds –60 dB, reducing jitter contribution from noisy DC/DC converters.

Is the FS pin of 552CH000118DG actively driven or pulled internally?

The FS pin of 552CH000118DG includes an internal 17 kΩ pull-up resistor to VDD, as documented in Table 11 and Section 3 of the datasheet. It requires no external biasing: logic low (≤0.5 V) selects the first frequency (125 MHz), and logic high (≥0.75×VDD) selects the second (156.25 MHz). The pin is TTL/CMOS compatible and draws negligible current - enabling direct connection to FPGA GPIO or dedicated frequency select lines.