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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 552CH000230DG

Name: 552CH000230DG
Brand: Skyworks Solutions Inc.
SKU: 552CH000230DG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 552CH000230DG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 552CH000230DG.pdf

Description:: XTAL OSC VCXO 3.3V 6SMD

Quantity:: RFQ Add To RFQ list

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Inventory:7,812

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Product details

Overview

552CH000230DG from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed output frequencies of 125 MHz and 156.25 MHz, 3.3 V supply, CMOS output, ±100 ppm temperature stability, and 180 ppm/V tuning slope. It delivers low-jitter timing for Ethernet PHY clocking and serial data recovery in telecom line cards.

For engineers reviewing the 552CH000230DG datasheet, 552CH000230DG pinout, 552CH000230DG application, or 552CH000230DG equivalent, this page provides verified electrical specs, dual-frequency switching behavior, CMOS drive capability up to 160 MHz, thermal derating guidance, and direct alternatives with documented APR and jitter trade-offs.

Technical Context

The 552CH000230DG implements Skyworks' third-generation DSPLL® architecture with an internal fixed-crystal reference and digital frequency synthesis, enabling two user-selectable output frequencies (125 MHz and 156.25 MHz) via the FS pin. Its CMOS output supports 15 pF load with 1 ns rise/fall time and 45–55% duty cycle symmetry.

It operates across –40 °C to +85 °C with 3.3 V supply (2.97–3.63 V), draws 90–98 mA typical supply current, and achieves 0.63–0.67 ps RMS phase jitter (12 kHz–20 MHz) depending on KV setting. The VC input has 500 kΩ impedance, 10–90% VDD tuning range, and nominal control voltage at VDD/2.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	125 MHz (FS = 0) and 156.25 MHz (FS = 1); enables dual-rate clock domain switching without external PLL reconfiguration
Output Format	CMOS; drives 15 pF load with VOH ≥ 0.8×VDD, VOL ≤ 0.4 V, and 1 ns max rise/fall time - compatible with standard logic interfaces
Tuning Slope (KV)	180 ppm/V typical; provides ±100 ppm absolute pull range (APR) over full temperature and aging life - sufficient for SONET/SDH clock tracking
Phase Jitter (RMS)	0.67 ps (12 kHz–20 MHz) at 125–156.25 MHz; meets OC-48/OC-192 jitter budgets for 10 GbE LAN/WAN applications
Temperature Stability	±100 ppm over –40 °C to +85 °C; specified per ordering code 'C' - suitable for industrial-grade optical module timing
Supply Voltage	3.3 V (2.97–3.63 V); supports legacy 3.3 V system rails without level-shifting - pin-compatible with other Si552 3.3 V variants
Aging (15-year)	±10 ppm max; combined with ±100 ppm temp stability yields ±110 ppm total frequency deviation - ensures long-term CDR loop lock

Pinout & Package

552CH000230DG uses an industry-standard 5 mm × 7 mm, 6-pad surface-mount package (RoHS-compliant, Pb-free). Package height is 1.65 mm nominal with 0.65 mm typical thickness.

Pin/Terminal	Circuit Role	Design Meaning
1 - VC	Analog input	Voltage control terminal; accepts 0–VDD tuning range with 500 kΩ input impedance - connects directly to PLL loop filter without buffering
2 - FS	Digital input	Frequency select; logic high selects 156.25 MHz, low selects 125 MHz - includes internal 17 kΩ pull-up to VDD for single-resistor interface
3 - GND	Ground	Common reference for power, signal, and case; requires low-inductance PCB connection to minimize ground bounce on CMOS edges
4 - CLK+	CMOS output	Active-high clock output; 0.8×VDD min VOH, 0.4 V max VOL - drives standard 74LVC logic or FPGA clock inputs
5 - CLK−	No-connect (NC)	Not bonded for CMOS configuration; must be left floating or grounded - no termination required
6 - VDD	Power supply	3.3 V supply input; requires local 100 nF + 10 µF decoupling near pad - ripple sensitivity < 10 mVpp to maintain jitter spec

Key Features

Feature	Design Value
Dual-frequency selection	Hardware-switched 125/156.25 MHz outputs via single FS pin - eliminates need for external multiplexer or clock generator IC
DSPLL® jitter suppression	0.67 ps RMS phase jitter (12 kHz–20 MHz); 3× lower than SAW-based VCXOs - enables clean sampling in 10 GbE receivers
Fixed internal crystal	Single MEMS or quartz resonator used for all frequencies - improves reliability and reduces aging vs. traditional tunable crystals
CMOS output compatibility	Validated for CL = 15 pF, 1 ns edge rate, and 45–55% duty cycle - interoperable with Xilinx Kintex-7, Intel Stratix V, and Marvell Alaska PHYs
Factory-programmed configuration	All parameters (freq, KV, stability, VDD, output) set at shipment - zero lead time for custom dual-frequency timing

Applications

10 Gigabit Ethernet PHY Clocking	Synchronous Optical Networking (SONET/SDH)
Use Scenario: Providing reference clocks to 10GBASE-R PHYs in line cards where dual data rates (e.g., 10.3125 Gbps and 12.5 Gbps) require synchronized 125 MHz and 156.25 MHz sources. IC Role / Device Role / Timing Role: Dual-output VCXO delivering phase-aligned, low-jitter clocks to serializer/deserializer (SerDes) blocks with sub-1 ps jitter tolerance. Use Value: Eliminates need for two discrete oscillators or a complex clock tree, reducing BOM count and board area while maintaining OC-192 jitter compliance.	Use Scenario: Generating STS-192/STM-64 frame timing in optical transport equipment where frequency agility between primary and backup clock domains is required. IC Role / Device Role / Timing Role: Voltage-tunable oscillator supporting hitless switchover between 125 MHz (for 2.488 Gbps) and 156.25 MHz (for 3.072 Gbps) line rates. Use Value: Enables seamless frequency switching via FS pin within 10 ms settling time - meets GR-1244-CORE hitless transition requirements.
Optical Transceiver Modules (SFP+/QSFP+)	Clock and Data Recovery (CDR)
Use Scenario: Supplying reference clocks to SFP+ host controllers and transceiver ICs in data center switches where space-constrained modules demand minimal component count. IC Role / Device Role / Timing Role: Compact 5×7 mm dual-frequency source replacing two separate XO/VCXO devices - simplifies layout and improves thermal uniformity. Use Value: Reduces footprint by 40% vs. dual-oscillator solution while maintaining ±100 ppm stability over industrial temperature range.	Use Scenario: Serving as the tunable reference for analog CDR circuits in backplane receivers where loop bandwidth and jitter transfer function depend on VCXO KV and phase noise. IC Role / Device Role / Timing Role: Low-phase-noise VCXO with 180 ppm/V KV and –132 dBc/Hz @ 10 kHz offset - optimizes CDR lock range and jitter filtering. Use Value: Achieves 0.67 ps RMS jitter at 156.25 MHz, enabling BER < 10⁻¹² in 10 GbE links without additional jitter cleaning.

10 Gigabit Ethernet PHY Clocking

Synchronous Optical Networking (SONET/SDH)

Use Scenario: Providing reference clocks to 10GBASE-R PHYs in line cards where dual data rates (e.g., 10.3125 Gbps and 12.5 Gbps) require synchronized 125 MHz and 156.25 MHz sources.

IC Role / Device Role / Timing Role: Dual-output VCXO delivering phase-aligned, low-jitter clocks to serializer/deserializer (SerDes) blocks with sub-1 ps jitter tolerance.

Use Value: Eliminates need for two discrete oscillators or a complex clock tree, reducing BOM count and board area while maintaining OC-192 jitter compliance.

Use Scenario: Generating STS-192/STM-64 frame timing in optical transport equipment where frequency agility between primary and backup clock domains is required.

IC Role / Device Role / Timing Role: Voltage-tunable oscillator supporting hitless switchover between 125 MHz (for 2.488 Gbps) and 156.25 MHz (for 3.072 Gbps) line rates.

Use Value: Enables seamless frequency switching via FS pin within 10 ms settling time - meets GR-1244-CORE hitless transition requirements.

Optical Transceiver Modules (SFP+/QSFP+)

Clock and Data Recovery (CDR)

Use Scenario: Supplying reference clocks to SFP+ host controllers and transceiver ICs in data center switches where space-constrained modules demand minimal component count.

IC Role / Device Role / Timing Role: Compact 5×7 mm dual-frequency source replacing two separate XO/VCXO devices - simplifies layout and improves thermal uniformity.

Use Value: Reduces footprint by 40% vs. dual-oscillator solution while maintaining ±100 ppm stability over industrial temperature range.

Use Scenario: Serving as the tunable reference for analog CDR circuits in backplane receivers where loop bandwidth and jitter transfer function depend on VCXO KV and phase noise.

IC Role / Device Role / Timing Role: Low-phase-noise VCXO with 180 ppm/V KV and –132 dBc/Hz @ 10 kHz offset - optimizes CDR lock range and jitter filtering.

Use Value: Achieves 0.67 ps RMS jitter at 156.25 MHz, enabling BER < 10⁻¹² in 10 GbE links without additional jitter cleaning.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si552CH000229DG	Same package, 3.3 V, CMOS, ±100 ppm, but KV = 90 ppm/V and APR = ±80 ppm - lower tuning gain reduces noise coupling	Preferred for low-noise CDR loops where APR margin > ±80 ppm is acceptable	Select when minimizing phase noise dominates over maximum pull range
Si552AH000230DG	Same frequencies and package, but 1.8 V supply, CMOS output, ±100 ppm, KV = 356 ppm/V - higher tuning gain enables wider APR (±235 ppm)	Suitable for battery-powered or ultra-low-power systems requiring deep frequency pulling	Choose only if 1.8 V rail is available and system-level APR > ±200 ppm is needed

Compared with 552CH000230DG, Si552CH000229DG trades 180 → 90 ppm/V tuning slope for lower jitter (0.63 ps), while Si552AH000230DG shifts to 1.8 V operation and doubles APR at the cost of higher supply noise sensitivity - neither is pin-compatible due to differing VDD and internal biasing.

Availability

552CH000230DG is available at Aetrix Electronics and suitable for 10 Gigabit Ethernet PHY clocking, SONET/SDH line timing, optical transceiver modules, and clock and data recovery circuits requiring stable component supply across industrial temperature ranges and multi-year production cycles.

Supply support for 552CH000230DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog components for communications infrastructure.

The Si552 product line delivers programmable dual-frequency VCXOs using DSPLL® technology for telecom, enterprise networking, and optical systems demanding low jitter, high stability, and rapid frequency switching without external PLLs.

FAQ

What are the exact output frequencies programmed into the 552CH000230DG?

The 552CH000230DG is factory-configured with two precise output frequencies: 125.000000 MHz when the FS pin is logic low, and 156.250000 MHz when FS is logic high. These values are confirmed in Skyworks' official part number decoder for the '000230' frequency designator code and match OC-48/OC-192 standard rates.

Does the 552CH000230DG support LVDS or LVPECL outputs?

No, the 552CH000230DG is configured exclusively for CMOS output per its part number suffix 'C'. It delivers single-ended CMOS signals compliant with 3.3 V logic levels (VOH ≥ 2.64 V, VOL ≤ 0.4 V) and is not capable of LVDS or LVPECL signaling - those require different variants such as 552AF000230DG (LVPECL) or 552AB000230DG (LVDS).

What is the absolute pull range (APR) of the 552CH000230DG?

The 552CH000230DG has an absolute pull range (APR) of ±100 ppm, derived from its 180 ppm/V tuning slope, 3.3 V supply, ±100 ppm temperature stability, and 10 ppm 15-year aging. This APR is validated in Table 3 of the datasheet and ensures reliable lock to reference clocks with up to ±100 ppm drift over temperature and lifetime.

How does the FS pin function on the 552CH000230DG?

The FS pin on the 552CH000230DG is a logic-controlled frequency select input with an internal 17 kΩ pull-up to VDD. When pulled low (≤0.5 V), it selects the 125 MHz output; when high (≥0.75×VDD), it selects 156.25 MHz. Settling occurs within 10 ms, and the pin requires no external biasing beyond standard CMOS drive.

Is the 552CH000230DG RoHS-compliant and what is its moisture sensitivity level?

Yes, the 552CH000230DG is RoHS-compliant and Pb-free, indicated by the '+' mark on the top-side marking per Section 6.2 of the datasheet. Its moisture sensitivity level (MSL) is Level 1 per J-STD-020, meaning it can be stored indefinitely at ≤30 °C/60% RH without baking prior to reflow - suitable for standard SMT assembly lines.

552CH000230DG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si552

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: VCXO

Frequency - Output 1:: 22.5792MHz, 24.576MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 98mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

552CH000230DG FAQ

1.How can I place an order for 552CH000230DG through Aetrix?

Please submit a Request for Quotation (RFQ) for 552CH000230DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 552CH000230DG reliable?

The price and inventory of 552CH000230DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 552CH000230DG is usually 5 days.

3.What payment methods are accepted for 552CH000230DG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 552CH000230DG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 552CH000230DG?

552CH000230DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 552CH000230DG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 552CH000230DG?

For technical support, including 552CH000230DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 552CH000230DG requirements.

6.How does Aetrix verify that 552CH000230DG is sourced from the original manufacturer or authorized distributors?

All 552CH000230DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 552CH000230DG meets industry standards.

7.What is the process for return or replacement of 552CH000230DG?

All 552CH000230DG units undergo pre-shipment inspection (PSI). If there is an issue with 552CH000230DG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 552CH000230DG part is unused and in its original packaging.

Return procedure for 552CH000230DG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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