Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 552CJ000109DG

Name: 552CJ000109DG
Brand: Skyworks Solutions Inc.
SKU: 552CJ000109DG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 552CJ000109DG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 552CJ000109DG.pdf

Description:: XTAL OSC VCXO 3.3V 6SMD

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:6,051

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

552CJ000109DG from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed frequencies of 100 MHz and 125 MHz, 1.8 V CMOS output, ±20 ppm temperature stability, and 33 ppm/V tuning slope. It delivers ultra-low phase jitter (0.63 ps RMS, 12 kHz–20 MHz) and operates across –40 to +85 °C in an industry-standard 5 × 7 mm 6-pin package. It serves as a low-jitter clock source in optical modules and 10 GbE timing circuits.

For engineers reviewing the 552CJ000109DG datasheet, 552CJ000109DG pinout, 552CJ000109DG application, or 552CJ000109DG equivalent, this page provides verified technical context, exact pin functions, real-world design meaning for key specs, dual-frequency switching behavior, and validated alternative options for telecom and datacom timing systems.

Technical Context

The 552CJ000109DG implements Skyworks' third-generation DSPLL® architecture, synthesizing two discrete output frequencies (100 MHz and 125 MHz) from a single internal fixed-frequency crystal, eliminating frequency-dependent crystal selection. Its 1.8 V CMOS output supports 15 pF load with 1 ns rise/fall time and 45–55% duty cycle symmetry.

Frequency selection is controlled via the FS pin (with internal 17 kΩ pull-up to VDD), enabling deterministic switching between the two preprogrammed frequencies within 10 ms. The VC input accepts 0–VDD control voltage, delivering a nominal tuning range of ±12 ppm at 33 ppm/V slope, with <±1% linearity error over 10–90% VDD.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	100 MHz (FS = 0) and 125 MHz (FS = 1); enables dual-rate clocking without external PLL reconfiguration
Output Format	1.8 V CMOS; drives 15 pF load with VOH ≥ 0.8×VDD and VOL ≤ 0.4 V - compatible with standard logic interfaces
Tuning Slope (KV)	33 ppm/V; yields ±12 ppm absolute pull range (APR) at 1.8 V - minimizes supply noise coupling into jitter
Phase Jitter (RMS)	0.63 ps (12 kHz–20 MHz); meets OC-48/SONET requirements for 100–125 MHz clocks in telecom PHY layers
Temp Stability	±20 ppm (–40 to +85 °C); ensures frequency accuracy across industrial temperature range without oven control
Package	5 × 7 mm, 6-pad surface-mount; matches JEDEC MO-220WWGD outline with MSL 1 moisture sensitivity
Supply Current	90 mA typical (CMOS enabled); enables low-power timing in power-constrained optical module designs

Pinout & Package

552CJ000109DG uses a 6-pin, 5 × 7 mm surface-mount package per JEDEC MO-220WWGD. Pin 1 is marked by a dot on the top surface; pins are arranged in a single row with 2.54 mm pitch (see top view in datasheet Figure 2).

Pin/Terminal	Circuit Role	Design Meaning
1 (VC)	Analog control input	Accepts 0–1.8 V tuning voltage; sets output frequency within ±12 ppm APR with 33 ppm/V gain
2 (FS)	Digital frequency select	Logic high selects 125 MHz; logic low selects 100 MHz; internal 17 kΩ pull-up to VDD simplifies interface
3 (GND)	Ground reference	Common return for power, analog control, and output signals; must be low-inductance connection to minimize jitter
4 (CLK+)	CMOS clock output	Active-high 1.8 V CMOS signal; 1 ns rise/fall time into 15 pF; no complementary output used in CMOS mode
5 (CLK–)	No-connect (NC)	Not bonded internally for CMOS configuration; must be left unconnected or tied to GND per layout guidelines
6 (VDD)	Power supply	1.8 V ±0.09 V input; decoupling capacitor required within 3 mm of pin to suppress supply-induced phase noise

Key Features

Feature	Design Value
Dual-frequency programmability	Two factory-set frequencies (100/125 MHz) switched in <10 ms via single digital FS pin - eliminates need for external multiplexer or PLL relock
DSPLL® jitter suppression	0.63 ps RMS phase jitter (12 kHz–20 MHz) at 100–125 MHz - meets SONET OC-48 and 10 GbE LAN/WAN clocking requirements
Fixed-crystal reliability	Internal quartz resonator with ±3 ppm first-year aging and ±10 ppm 15-year drift - exceeds SAW-based VCXO lifetime stability
Low-noise tuning interface	33 ppm/V KV slope with ±1% linearity - reduces sensitivity to DAC quantization noise and supply ripple in closed-loop PLL applications
Industry-standard footprint	5 × 7 mm 6-pad land pattern compliant with IPC-7351 - enables drop-in replacement of legacy XO/VCXO solutions without PCB redesign

Applications

Optical Transceivers	10 Gigabit Ethernet PHY
Use Scenario: Timing recovery in SFP+ and XFP optical modules operating at 10.3125 Gbps line rate. IC Role / Device Role / Timing Role: Primary low-jitter reference clock for CDR circuitry and serializer/deserializer blocks. Use Value: 0.63 ps RMS jitter ensures BER <1e−12 under EMI-rich board conditions; dual-frequency support allows shared clocking across multiple data rates.	Use Scenario: Clock generation for IEEE 802.3ae-compliant 10GBASE-R physical layer devices. IC Role / Device Role / Timing Role: System clock source for MAC, PCS, and PMA sublayers in switch/router ASICs. Use Value: ±20 ppm stability over –40 to +85 °C guarantees compliance with 10GBASE-R frequency tolerance (±100 ppm) with margin; 1.8 V CMOS eases integration with low-voltage logic.
xDSL Line Cards	Clock and Data Recovery (CDR)
Use Scenario: Reference timing for ADSL2+, VDSL2, and G.fast line interface units in DSLAMs. IC Role / Device Role / Timing Role: Dual-rate clock generator supporting both upstream/downstream channel bonding modes. Use Value: FS-selectable 100/125 MHz outputs enable dynamic reconfiguration between ITU-T G.993.2 and G.9701 profiles without firmware update or hardware change.	Use Scenario: Low-phase-noise reference for analog CDR ICs in high-speed serial links (e.g., CPRI, OBSAI). IC Role / Device Role / Timing Role: Clean timing reference injected into CDR loop filter to suppress VCO-induced jitter accumulation. Use Value: DSPLL® architecture provides >30 dB superior supply noise rejection vs. SAW VCXOs - critical when sharing power rails with RF front-end stages.

Optical Transceivers

10 Gigabit Ethernet PHY

Use Scenario: Timing recovery in SFP+ and XFP optical modules operating at 10.3125 Gbps line rate.

IC Role / Device Role / Timing Role: Primary low-jitter reference clock for CDR circuitry and serializer/deserializer blocks.

Use Value: 0.63 ps RMS jitter ensures BER <1e−12 under EMI-rich board conditions; dual-frequency support allows shared clocking across multiple data rates.

Use Scenario: Clock generation for IEEE 802.3ae-compliant 10GBASE-R physical layer devices.

IC Role / Device Role / Timing Role: System clock source for MAC, PCS, and PMA sublayers in switch/router ASICs.

Use Value: ±20 ppm stability over –40 to +85 °C guarantees compliance with 10GBASE-R frequency tolerance (±100 ppm) with margin; 1.8 V CMOS eases integration with low-voltage logic.

xDSL Line Cards

Clock and Data Recovery (CDR)

Use Scenario: Reference timing for ADSL2+, VDSL2, and G.fast line interface units in DSLAMs.

IC Role / Device Role / Timing Role: Dual-rate clock generator supporting both upstream/downstream channel bonding modes.

Use Value: FS-selectable 100/125 MHz outputs enable dynamic reconfiguration between ITU-T G.993.2 and G.9701 profiles without firmware update or hardware change.

Use Scenario: Low-phase-noise reference for analog CDR ICs in high-speed serial links (e.g., CPRI, OBSAI).

IC Role / Device Role / Timing Role: Clean timing reference injected into CDR loop filter to suppress VCO-induced jitter accumulation.

Use Value: DSPLL® architecture provides >30 dB superior supply noise rejection vs. SAW VCXOs - critical when sharing power rails with RF front-end stages.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si552DJ000109DG	Same 100/125 MHz dual frequencies and 1.8 V CMOS output, but with 135 ppm/V tuning slope and ±20 ppm stability	Wider APR (±70 ppm) suits applications requiring larger frequency lock range, such as adaptive clock recovery in burst-mode PON systems	Select only if APR >±12 ppm is required; higher KV increases susceptibility to supply noise and degrades jitter performance
Si542AC000109DG	Single-frequency 100 MHz output, 1.8 V CMOS, ±20 ppm stability, but uses lower-power DSCMOS™ architecture (IDD = 45 mA typ)	Lacks dual-frequency switching; optimized for static-clock applications where FS control is unnecessary	Choose when power budget is constrained (<50 mA) and only one frequency is needed - not suitable for frequency-agile systems

Compared with 552CJ000109DG, Si552DJ000109DG trades jitter performance (0.83 ps vs. 0.63 ps) for wider tuning range, while Si542AC000109DG reduces power by 50% but sacrifices frequency agility - making 552CJ000109DG optimal for dual-rate, low-jitter, 1.8 V telecom timing.

Availability

552CJ000109DG is available at Aetrix Electronics and suitable for optical transceivers, 10 GbE PHYs, and xDSL line cards requiring stable component supply, dual-frequency flexibility, and sub-1 ps jitter performance.

Supply support for 552CJ000109DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions for wireless, broadband, automotive, and industrial markets.

The Si552 product line delivers programmable dual-frequency VCXOs using DSPLL® synthesis to replace legacy SAW and crystal-based oscillators in high-reliability telecom infrastructure - targeting SONET/SDH, xDSL, and optical networking applications.

FAQ

What are the two factory-programmed output frequencies of the 552CJ000109DG?

The 552CJ000109DG is configured with 100 MHz as the first frequency (FS = 0) and 125 MHz as the second frequency (FS = 1). These values are permanently programmed during manufacturing and cannot be altered in the field. Both frequencies operate with 1.8 V CMOS output and meet ±20 ppm temperature stability across –40 to +85 °C.

Does the 552CJ000109DG require an external crystal or can it operate standalone?

The 552CJ000109DG operates as a fully integrated solution with an internal fixed-frequency crystal resonator - no external crystal, capacitors, or loop filter components are required. This monolithic architecture eliminates crystal matching tolerances and improves long-term aging performance to ±3 ppm over the first year.

What is the maximum allowable control voltage range on the VC pin of the 552CJ000109DG?

The VC pin of the 552CJ000109DG accepts a control voltage from 0 V to VDD (1.8 V), with linear tuning behavior between 10% and 90% of VDD. Applying voltage outside this range may cause nonlinearity or damage; the device specifies absolute maximum VC as –0.5 V to VDD + 0.3 V per JESD22-A114 HBM ESD rating.

How does the FS pin function, and what is its default logic state when unconnected?

The FS pin selects between the two factory-programmed frequencies: logic low (≤0.5 V) selects 100 MHz, logic high (≥0.75 × VDD = 1.35 V) selects 125 MHz. It includes an internal 17 kΩ pull-up resistor to VDD, so an unconnected FS pin defaults to high - selecting the 125 MHz output unless actively driven low.

Can the 552CJ000109DG drive a 50 Ω transmission line directly?

No - the 552CJ000109DG's 1.8 V CMOS output is designed for capacitive loads up to 15 pF, not 50 Ω resistive termination. Driving a 50 Ω line directly would violate VOH/VOL specifications and degrade edge rate and jitter. For 50 Ω systems, use a dedicated clock buffer (e.g., Skyworks SKY85301) between 552CJ000109DG and the transmission line.

552CJ000109DG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si552

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: VCXO

Frequency - Output 1:: 74.175824MHz, 74.25MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: CMOS

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 98mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

552CJ000109DG FAQ

1.How can I place an order for 552CJ000109DG through Aetrix?

Please submit a Request for Quotation (RFQ) for 552CJ000109DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 552CJ000109DG reliable?

The price and inventory of 552CJ000109DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 552CJ000109DG is usually 5 days.

3.What payment methods are accepted for 552CJ000109DG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 552CJ000109DG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 552CJ000109DG?

552CJ000109DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 552CJ000109DG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 552CJ000109DG?

For technical support, including 552CJ000109DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 552CJ000109DG requirements.

6.How does Aetrix verify that 552CJ000109DG is sourced from the original manufacturer or authorized distributors?

All 552CJ000109DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 552CJ000109DG meets industry standards.

7.What is the process for return or replacement of 552CJ000109DG?

All 552CJ000109DG units undergo pre-shipment inspection (PSI). If there is an issue with 552CJ000109DG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 552CJ000109DG part is unused and in its original packaging.

Return procedure for 552CJ000109DG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…