Skyworks Solutions Inc. 552CM000109DG
- Part No.:
- 552CM000109DG
- Manufacturer:
- Skyworks Solutions Inc.
- Category:
- Pin Configurable/Selectable Oscillators
- Package:
- 6-SMD, No Lead
- Datasheet:
-
552CM000109DG.pdf
- Description:
- XTAL OSC VCXO 3.3V 6SMD
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
552CM000109DG from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed output frequencies of 10 MHz and 109 MHz, 3.3 V CMOS output, ±50 ppm temperature stability, 90 ppm/V tuning slope, and operation from –40 °C to +85 °C in an industry-standard 5 × 7 mm 6-pin package. It delivers low-jitter timing for clock and data recovery in xDSL and optical modules.
For engineers reviewing the 552CM000109DG datasheet, 552CM000109DG pinout, 552CM000109DG application, or 552CM000109DG equivalent, this page provides verified electrical specifications, dual-frequency switching behavior, CMOS output drive capability up to 160 MHz, VC control voltage linearity, and thermal performance under industrial ambient conditions.
Technical Context
The 552CM000109DG implements Skyworks' third-generation DSPLL® architecture with an internal fixed crystal reference, enabling two user-selectable output frequencies (10 MHz and 109 MHz) via the FS pin. Its analog VC input accepts 0–VDD control voltage with 90 ppm/V tuning slope and ±5% incremental linearity over 10–90% VDD range.
This VCXO supports CMOS output with 0.8×VDD VOH and 0.4 V VOL into 32 mA loads, 1 ns rise/fall time at CL = 15 pF, and 45–55% duty cycle symmetry. Power-up time is ≤10 ms, and frequency settling after FS transition is ≤10 ms - critical for dynamic clock source selection in telecom PHY layers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Nominal Frequencies | 10 MHz (FS = 0) and 109 MHz (FS = 1); both factory-programmed and stable across –40 to +85 °C |
| Output Format | CMOS; compatible with standard logic interfaces, supports 160 MHz max frequency, 32 mA drive strength |
| Supply Voltage | 3.3 V ±10%; enables direct integration with 3.3 V system rails without LDO overhead |
| Tuning Slope (KV) | 90 ppm/V typical; provides ±80 ppm APR at 3.3 V while balancing jitter vs. pull range trade-off |
| Temperature Stability | ±50 ppm over –40 to +85 °C; meets SONET/SDH OC-3 and xDSL timing margin requirements |
| Phase Jitter (RMS) | 0.67 ps (12 kHz–20 MHz) at 109 MHz, KV = 90 ppm/V; sufficient for 10 GbE LAN/WAN CDR lock acquisition |
| Aging (15-year) | ±10 ppm; ensures long-term frequency accuracy without field recalibration in deployed infrastructure |
Pinout & Package
552CM000109DG is housed in an industry-standard RoHS-compliant 5 × 7 mm, 6-pad surface-mount package with exposed pad thermal path (θJA = 84.6 °C/W). Pin 1 is marked by a dot; top marking includes "552", revision "D", and trace code.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - VC | Analog control input | Accepts 0–3.3 V tuning voltage; 500 kΩ input impedance; nominal center at 1.65 V for fO |
| 2 - FS | Digital frequency select | Active-high logic input with 17 kΩ internal pull-up to VDD; selects 10 MHz (FS = 0) or 109 MHz (FS = 1) |
| 3 - GND | Ground reference | Common return for power, output, and control paths; must be low-inductance connection to minimize noise coupling |
| 4 - CLK+ | CMOS clock output | Single-ended 3.3 V CMOS signal; VOH ≥ 2.64 V, VOL ≤ 0.4 V at 32 mA; 1 ns edge rate into 15 pF |
| 5 - CLK− | No-connect (NC) | Not bonded for CMOS output configuration; must be left floating or grounded per layout guidelines |
| 6 - VDD | Power supply | 3.3 V ±10% input; decoupling required within 5 mm of pin; supplies DSPLL core and output buffer |
Key Features
| Feature | Design Value |
|---|---|
| Dual-frequency selection via FS pin | Enables seamless switching between 10 MHz reference and 109 MHz data-path clock without external multiplexer or PLL relock |
| DSPLL®-based synthesis | Eliminates need for multiple crystals; achieves <0.7 ps RMS jitter at 109 MHz using single internal fixed-frequency resonator |
| Factory-configured parameters | Frequency pair, output format, supply voltage, KV, and stability are programmed before shipment - no post-silicon configuration required |
| CMOS output compatibility | Meets JEDEC Std. 22.01 for 3.3 V logic; drives standard FPGA/ASIC clock inputs with 15 pF load and 1 ns edges |
| Industrial temperature range | Guaranteed operation from –40 °C to +85 °C with full specification compliance - suitable for uncontrolled outdoor telecom cabinets |
Applications
| SONET/SDH Line Cards | xDSL Central Office Equipment |
|---|---|
|
Use Scenario: Timing recovery and frame synchronization in OC-3/OC-12 line interface units. IC Role / Device Role / Timing Role: Dual-frequency VCXO providing 10 MHz system reference and 109 MHz payload clock synchronized to incoming line rate. Use Value: Enables deterministic frequency switching during protection switching events with ≤10 ms settling time and ±50 ppm stability over temperature. |
Use Scenario: Multi-rate DSLAM timing for ADSL2+, VDSL2, and G.fast line cards operating in shared infrastructure. IC Role / Device Role / Timing Role: Clock source for analog front-end (AFE) and digital signal processor (DSP), selectable between baseband (10 MHz) and high-speed (109 MHz) modes. Use Value: Reduces BOM count by replacing two discrete oscillators; maintains <0.67 ps phase jitter at 109 MHz for clean symbol timing in multi-tone systems. |
| Optical Transceivers (SFP+) | Clock and Data Recovery (CDR) |
|
Use Scenario: Low-power, compact timing solution for 10 GbE SFP+ pluggable modules with thermal constraints. IC Role / Device Role / Timing Role: Primary clock generator for serializer/deserializer (SerDes) and microcontroller subsystems. Use Value: 5 × 7 mm footprint matches industry-standard oscillator footprints; CMOS output eliminates need for level-shifting buffers. |
Use Scenario: Reference clock generation in CDR circuits requiring fast frequency agility and low integrated jitter. IC Role / Device Role / Timing Role: Voltage-tunable oscillator feeding phase detector loop; FS pin allows dynamic reconfiguration of loop bandwidth. Use Value: 90 ppm/V KV and ±80 ppm APR support wide capture range while maintaining sub-1 ps RMS jitter for reliable lock acquisition. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-frequency VCXO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Si552CM000108DG | Same package and CMOS output, but programmed for 644.53 MHz / 693.48 MHz pair instead of 10/109 MHz | Targets high-speed serial links (e.g., 10G Ethernet PHY), not baseband or low-frequency timing | Select only if dual-frequency requirement exceeds 160 MHz; incompatible for 10 MHz reference use cases |
| Si542BA000109DG | Single-output XO (not VCXO); no VC or FS pins; ±20 ppm stability; same 10/109 MHz frequencies | Used where voltage tuning and frequency switching are unnecessary - e.g., static clock trees | Choose when absolute frequency stability > tuning flexibility; lacks VCXO functionality required for PLL tracking |
Compared with 552CM000109DG, Si552CM000108DG serves higher-frequency serial applications but cannot replace the 10/109 MHz pair, while Si542BA000109DG offers tighter stability but eliminates voltage control and dual-frequency switching - making it unsuitable for adaptive timing architectures.
Availability
552CM000109DG is available at Aetrix Electronics and suitable for SONET/SDH line cards, xDSL central office equipment, and optical transceivers requiring stable component supply, guaranteed long-term availability, and RoHS-compliant packaging.
Supply support for 552CM000109DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products.
The Si552 product line is designed for high-performance, programmable timing in communications infrastructure - delivering dual-frequency agility, ultra-low jitter, and factory-configurable parameters to replace legacy SAW- and crystal-based VCXOs.
FAQ
What are the exact factory-programmed frequencies for 552CM000109DG?
The 552CM000109DG is factory-programmed for two precise output frequencies: 10.000000 MHz when FS = 0, and 109.000000 MHz when FS = 1. These values are laser-trimmed and verified during final test; no field programming is possible. Both frequencies maintain ±50 ppm stability across –40 to +85 °C and exhibit <0.67 ps RMS phase jitter (12 kHz–20 MHz) at 109 MHz with KV = 90 ppm/V.
Does 552CM000109DG support LVDS or LVPECL outputs?
No, 552CM000109DG is configured exclusively for CMOS output, as indicated by the "C" in the second option code position of its part number. It delivers single-ended 3.3 V CMOS signals with VOH ≥ 2.64 V and VOL ≤ 0.4 V at 32 mA load. LVDS and LVPECL variants exist in the Si552 family (e.g., 552AFxxxxx), but 552CM000109DG does not include differential output circuitry - CLK− is a no-connect terminal.
What is the absolute pull range (APR) of 552CM000109DG?
The 552CM000109DG has a minimum absolute pull range (APR) of ±80 ppm at 3.3 V supply, calculated as (0.5 × 3.3 V × 90 ppm/V) − 50 ppm (stability) − 10 ppm (15-year aging). This APR enables reliable lock to reference clocks with up to ±80 ppm initial tolerance and drift over temperature and lifetime - sufficient for xDSL and SONET/SDH applications where master clock stability is ±50 ppm.
How does the FS pin function on 552CM000109DG?
The FS pin on 552CM000109DG is a digital input with an internal 17 kΩ pull-up to VDD. When pulled low (≤0.5 V), it selects the first frequency (10 MHz); when high (≥2.475 V), it selects the second (109 MHz). Frequency switching occurs within ≤10 ms, and the device maintains valid output during transition. No external pull-up resistor is required, and the pin is compatible with standard 3.3 V logic drivers.
Is 552CM000109DG compliant with lead-free and RoHS requirements?
Yes, 552CM000109DG is Pb-free and RoHS-compliant, as confirmed by Skyworks' documentation and indicated by the "+" mark in its top-side laser marking. It meets JEDEC J-STD-020C MSL 1 classification, supports Pb-free reflow profiles (peak 260 °C for 20–40 seconds), and passes MIL-STD-883F mechanical and environmental qualification tests including thermal shock, vibration, and moisture resistance.
552CM000109DG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Skyworks Solutions Inc.
- Series:
- Si552
- Package/Case:
- 6-SMD, No Lead
- Packaging:
- Strip
- Product Status:
- Active
- Base Resonator:
- Crystal
- Type:
- VCXO
- Frequency - Output 1:
- 74.175824MHz, 74.25MHz
- Frequency - Output 2:
- -
- Frequency - Output 3:
- -
- Frequency - Output 4:
- -
- Function:
- Enable/Disable
- Output:
- CMOS
- Voltage - Supply:
- 3.3V
- Frequency Stability:
- ±20ppm
- Operating Temperature:
- -40°C ~ 85°C
- Current - Supply (Max):
- 98mA
- Ratings:
- -
- Size / Dimension:
- 0.276" L x 0.197" W (7.00mm x 5.00mm)
- Height:
- 0.071" (1.80mm)
- Supplier Device Package:
- -
552CM000109DG FAQ
1.How can I place an order for 552CM000109DG through Aetrix?
Please submit a Request for Quotation (RFQ) for 552CM000109DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 552CM000109DG reliable?
The price and inventory of 552CM000109DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 552CM000109DG is usually 5 days.
3.What payment methods are accepted for 552CM000109DG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 552CM000109DG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 552CM000109DG?
552CM000109DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 552CM000109DG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 552CM000109DG?
For technical support, including 552CM000109DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 552CM000109DG requirements.
6.How does Aetrix verify that 552CM000109DG is sourced from the original manufacturer or authorized distributors?
All 552CM000109DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 552CM000109DG meets industry standards.
7.What is the process for return or replacement of 552CM000109DG?
All 552CM000109DG units undergo pre-shipment inspection (PSI). If there is an issue with 552CM000109DG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 552CM000109DG part is unused and in its original packaging.
Return procedure for 552CM000109DG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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