Skyworks Solutions Inc. 552FJ000109DGR

Overview

552FJ000109DGR from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed frequencies of 100 MHz and 125 MHz, 1.8 V CMOS output, ±20 ppm temperature stability, 33 ppm/V tuning slope, and operation from –40 °C to +85 °C in a 5 × 7 mm surface-mount package. It delivers low-jitter timing for clock-sensitive communication systems.

For engineers reviewing the 552FJ000109DGR datasheet, 552FJ000109DGR pinout, 552FJ000109DGR application, or 552FJ000109DGR equivalent, this page provides verified electrical specs, dual-frequency switching behavior, CMOS drive capability up to 160 MHz, jitter performance down to 0.63 ps RMS (12 kHz–20 MHz), and real-world supply noise rejection advantages over SAW-based VCXOs.

Technical Context

The 552FJ000109DGR implements Skyworks' 3rd-generation DSPLL® architecture to synthesize two precise output frequencies from a single internal fixed-crystal reference. Its dual-frequency selection is controlled by the FS pin, enabling seamless switching between 100 MHz and 125 MHz without external reconfiguration.

It features a 1.8 V CMOS output stage with rail-to-rail swing, 45–55% duty cycle symmetry, and tristate capability. The VC input accepts 0–1.8 V control voltage with 33 ppm/V tuning slope, delivering ±12 ppm absolute pull range (APR) across temperature and aging.

Key Specifications

Pinout & Package

552FJ000109DGR uses an industry-standard 6-pad, 5 × 7 mm surface-mount ceramic package (RoHS-compliant, MSL 1). Pin 1 is marked with a dot; mounting follows IPC-7351 land pattern guidelines.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Compared with Si552DJ000109DGR and Si542FJ000109DG, the 552FJ000109DGR uniquely balances 1.8 V CMOS compatibility, dual-frequency agility, and sub-0.65 ps jitter-making it optimal for space-constrained, multi-standard telecom PHYs where voltage scaling and flexibility are mandatory.

Availability

552FJ000109DGR is available at Aetrix Electronics and suitable for SONET/SDH line cards, xDSL central office equipment, and 10 GbE LAN/WAN switches requiring stable component supply, long-lifecycle support, and RoHS-compliant timing solutions.

Supply support for 552FJ000109DGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog ICs.

The Si552 product line delivers programmable, low-jitter VCXOs for high-speed communications infrastructure-designed to replace legacy SAW and crystal-based oscillators with superior stability, noise immunity, and configurability.

FAQ

What are the exact factory-programmed frequencies for 552FJ000109DGR?

The 552FJ000109DGR is programmed with two precise frequencies: 100.000000 MHz (selected when FS = 0) and 125.000000 MHz (selected when FS = 1). These values are permanently stored during manufacturing and cannot be altered in the field. Both frequencies meet ±20 ppm stability over –40 °C to +85 °C and exhibit 0.63 ps RMS phase jitter under standard test conditions.

Does 552FJ000109DGR support tristate functionality, and how is it implemented?

Yes, the 552FJ000109DGR supports output disable via its VC pin: driving VC below 0.5 V places the CMOS output into high-impedance (tristate) mode. This feature allows dynamic clock gating without external switches. During tristate, supply current drops to 60–75 mA, and the CLK+ output presents >100 MΩ impedance-enabling clean bus sharing in multi-oscillator systems.

What is the maximum capacitive load the 552FJ000109DGR CMOS output can drive reliably?

The 552FJ000109DGR CMOS output is characterized and guaranteed for reliable operation with a 15 pF load, achieving 1 ns rise/fall times and 45–55% duty cycle symmetry. Driving loads beyond 15 pF may degrade edge rate and jitter; for heavier loads, external buffer amplification is recommended. Layout best practices include short traces and minimized stub length to preserve signal integrity.

How does the 33 ppm/V tuning slope of 552FJ000109DGR affect its phase noise performance?

The 33 ppm/V tuning slope of the 552FJ000109DGR is specifically selected to minimize phase noise degradation while meeting the ±12 ppm APR requirement. Lower KV reduces sensitivity to supply and substrate noise-resulting in 0.63 ps RMS jitter (12 kHz–20 MHz), which is 30% lower than comparable 90 ppm/V variants. This makes it ideal for jitter-critical applications like 10 GbE CDR.

Is the 552FJ000109DGR pin-compatible with other Si552 variants in the same package?

Yes, all Si552 devices-including 552FJ000109DGR-share identical 6-pin, 5 × 7 mm footprint and pinout (VC, FS, GND, CLK+, CLK−, VDD). Mechanical and solder pad compatibility is guaranteed across voltage options (1.8/2.5/3.3 V) and output types (CMOS/LVPECL/LVDS/CML). However, CLK− is NC for CMOS variants like 552FJ000109DGR and must remain unconnected.