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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 554BM000159DGR

Name: 554BM000159DGR
Brand: Skyworks Solutions Inc.
SKU: 554BM000159DGR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 554BM000159DGR

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 8-SMD, No Lead

Datasheet:: 554BM000159DGR.pdf

Description:: XTAL OSC VCXO 3.3V 8SMD

Quantity:: RFQ Add To RFQ list

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Inventory:5,404

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Product details

Overview

554BM000159DGR from Skyworks Solutions is a quad-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed output frequencies of 155.52 MHz, 156.25 MHz, 159.375 MHz, and 161.1328125 MHz, 3.3 V LVDS output, ±50 ppm temperature stability, 90 ppm/V tuning slope, and operation from –40 °C to +85 °C in a 5 × 7 mm 8-pin surface-mount package. It delivers low-jitter clocking for telecom synchronization and serial data links.

For engineers reviewing the 554BM000159DGR datasheet, 554BM000159DGR pinout, 554BM000159DGR application, or 554BM000159DGR equivalent, this device supports frequency-selectable, low-phase-noise timing in SONET/SDH, 10GbE, and optical module designs where supply noise rejection and multi-rate flexibility are critical.

Technical Context

The 554BM000159DGR implements Skyworks' third-generation DSPLL® architecture, synthesizing four discrete output frequencies from a single internal fixed-frequency crystal reference. Its analog VC input accepts 0–VDD control voltage with 90 ppm/V tuning slope and ±30 ppm APR at 3.3 V, enabling precise PLL lock range tracking.

It integrates programmable OE polarity (active-high per ordering code 'B'), dual-bit FS[1:0] frequency selection, and LVDS differential outputs with 1.20 V nominal common-mode level, 0.7 VPP typical differential swing, and 45–55% duty cycle symmetry - all compliant with industry-standard 5 × 7 mm footprint and MSL 1 handling.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	155.52 MHz, 156.25 MHz, 159.375 MHz, 161.1328125 MHz - four factory-configured rates selectable via FS[1:0] pins
Output Format	LVDS - differential signaling with 100 Ω termination, enabling robust noise immunity in high-speed backplanes
Supply Voltage	3.3 V - supports standard logic rail with 2.97–3.63 V operating range and 120 mA typical supply current
Tuning Slope (KV)	90 ppm/V - provides ±30 ppm absolute pull range at 3.3 V, optimized for stable loop bandwidth in telecom PLLs
Temp Stability	±50 ppm over –40 °C to +85 °C - ensures frequency accuracy across industrial temperature extremes without recalibration
Phase Jitter (RMS)	0.37 ps (12 kHz–20 MHz) at 155.52 MHz - meets OC-48/SONET jitter compliance for synchronous Ethernet applications
Package	5 × 7 mm 8-pad surface-mount - industry-standard footprint compatible with automated SMT assembly and IPC-7351 land patterns

Pinout & Package

554BM000159DGR is housed in an industry-standard 5 × 7 mm, 8-pad surface-mount package with exposed thermal pad (not electrically connected). Pin 1 is marked by a dot on the top surface.

Pin/Terminal	Circuit Role	Design Meaning
1	VC	Analog control voltage input - accepts 0–3.3 V to adjust output frequency within ±30 ppm APR window
2	OE	Output enable (active-high) - drives CLK+/CLK– into high-impedance state when low, reducing system power during idle
3	GND	Electrical and case ground - serves as return path for all signals and power, requiring low-inductance PCB connection
4	CLK+	Differential clock output (LVDS) - delivers true-phase signal referenced to CLK– with 1.20 V common-mode level
5	CLK–	Differential clock output (LVDS) - complementary signal to CLK+, forming 100 Ω differential pair for EMI reduction
6	VDD	3.3 V power supply - must be decoupled with ≥10 µF bulk + 100 nF ceramic capacitor near pin for jitter suppression
7	FS[1]	Frequency select MSB - combined with FS[0], selects one of four preprogrammed output frequencies (00–11)
8	FS[0]	Frequency select LSB - latched on power-up or after OE toggle; no glitching during transitions

Key Features

Feature	Design Value
Quad-frequency DSPLL synthesis	Four factory-programmed frequencies (155.52/156.25/159.375/161.1328125 MHz) derived from single crystal - eliminates multiple XO BOMs
LVDS output interface	100 Ω differential termination support with 0.7 VPP swing and <350 ps rise/fall time - ensures signal integrity up to 160 MHz
90 ppm/V tuning slope	Optimized KV for telecom APR requirements - enables tight loop filter design while minimizing supply-induced jitter coupling
±50 ppm temp stability	Guaranteed frequency deviation over full –40 °C to +85 °C range - eliminates need for external compensation in outdoor/base station gear
Industry-standard 5 × 7 mm package	Drop-in replacement for legacy VCXOs - uses identical PCB land pattern and reflow profile per JEDEC J-STD-020C

Applications

SONET/SDH Line Cards	10GbE LAN/WAN PHY Timing
Use Scenario: Synchronous transport network equipment requiring precise 155.52 MHz and 622.08 MHz clock derivation with holdover capability. IC Role / Device Role / Timing Role: Primary VCXO providing four telecom-standard frequencies for framers, mappers, and SERDES clock recovery. Use Value: DSPLL-based jitter performance (0.37 ps RMS) meets GR-1244-CORE OC-48 mask, enabling bit-error-free operation over extended distances.	Use Scenario: High-density switch/router line cards needing flexible, low-jitter reference clocks for multiple 10GbE interfaces. IC Role / Device Role / Timing Role: Quad-frequency source supplying independent clocks to separate PHY lanes or retimers via FS[1:0] selection. Use Value: Single-device frequency agility reduces board space vs. discrete XO solutions while maintaining <1 ps period jitter (RMS).
Optical Transceivers (SFP+/QSFP)	Clock and Data Recovery (CDR) Systems
Use Scenario: Pluggable optical modules requiring compact, reliable timing with low phase noise for 10G–25G NRZ/PAM4 modulation. IC Role / Device Role / Timing Role: Low-power LVDS oscillator delivering 156.25 MHz or 159.375 MHz reference to CDR ICs and laser drivers. Use Value: 3.3 V LVDS drive strength and 0.37 ps phase jitter ensure clean sampling edges, directly improving BER margin in high-loss fiber links.	Use Scenario: FPGA- or ASIC-based CDR subsystems needing stable, tunable reference clocks for adaptive loop bandwidth control. IC Role / Device Role / Timing Role: Voltage-controlled reference generator synchronized to incoming data stream via VC input and PLL feedback. Use Value: 90 ppm/V KV and ±30 ppm APR allow precise lock range matching to data rate tolerance, minimizing loss-of-lock events.

SONET/SDH Line Cards

10GbE LAN/WAN PHY Timing

Use Scenario: Synchronous transport network equipment requiring precise 155.52 MHz and 622.08 MHz clock derivation with holdover capability.

IC Role / Device Role / Timing Role: Primary VCXO providing four telecom-standard frequencies for framers, mappers, and SERDES clock recovery.

Use Value: DSPLL-based jitter performance (0.37 ps RMS) meets GR-1244-CORE OC-48 mask, enabling bit-error-free operation over extended distances.

Use Scenario: High-density switch/router line cards needing flexible, low-jitter reference clocks for multiple 10GbE interfaces.

IC Role / Device Role / Timing Role: Quad-frequency source supplying independent clocks to separate PHY lanes or retimers via FS[1:0] selection.

Use Value: Single-device frequency agility reduces board space vs. discrete XO solutions while maintaining <1 ps period jitter (RMS).

Optical Transceivers (SFP+/QSFP)

Clock and Data Recovery (CDR) Systems

Use Scenario: Pluggable optical modules requiring compact, reliable timing with low phase noise for 10G–25G NRZ/PAM4 modulation.

IC Role / Device Role / Timing Role: Low-power LVDS oscillator delivering 156.25 MHz or 159.375 MHz reference to CDR ICs and laser drivers.

Use Value: 3.3 V LVDS drive strength and 0.37 ps phase jitter ensure clean sampling edges, directly improving BER margin in high-loss fiber links.

Use Scenario: FPGA- or ASIC-based CDR subsystems needing stable, tunable reference clocks for adaptive loop bandwidth control.

IC Role / Device Role / Timing Role: Voltage-controlled reference generator synchronized to incoming data stream via VC input and PLL feedback.

Use Value: 90 ppm/V KV and ±30 ppm APR allow precise lock range matching to data rate tolerance, minimizing loss-of-lock events.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-frequency VCXO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si552BM000159DGR	Same Si55x family, but dual-frequency (2 outputs) instead of quad; identical LVDS, 3.3 V, ±50 ppm, 90 ppm/V specs	Limited to two frequencies - insufficient for systems requiring four distinct rates like multi-protocol line cards	Select only if BOM simplification outweighs frequency flexibility; requires FS logic redesign
554BF000159DGR	Same quad-frequency configuration but with 2.5 V LVDS supply (not 3.3 V); otherwise identical stability, KV, and jitter	Requires 2.5 V rail and compatible IO standards - unsuitable for 3.3 V-only systems or mixed-voltage backplanes	Choose only when system-level power architecture mandates 2.5 V timing rails

Compared with 554BM000159DGR, the Si552BM000159DGR reduces frequency count but saves cost and layout area, while the 554BF000159DGR maintains full functionality at lower voltage - both require careful validation of supply compatibility and frequency coverage before substitution.

Availability

554BM000159DGR is available at Aetrix Electronics and suitable for SONET/SDH line cards, 10GbE networking hardware, and optical transceiver modules requiring stable component supply, long-lifecycle support, and RoHS-compliant timing solutions.

Supply support for 554BM000159DGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products for communications infrastructure and enterprise systems.

The Si554 product line delivers programmable, low-jitter VCXOs for telecom and datacom applications where multi-rate flexibility, supply noise immunity, and long-term frequency stability are essential - targeting SONET, Ethernet, and optical transport systems.

FAQ

What output frequencies are factory-programmed in the 554BM000159DGR?

The 554BM000159DGR is configured with four specific output frequencies: 155.52 MHz, 156.25 MHz, 159.375 MHz, and 161.1328125 MHz. These are permanently programmed at manufacture and selected via the FS[1:0] pins. No field reprogramming is possible - the frequencies are fixed per the part number's six-digit code '000159', which maps to this exact set in the Si554 frequency database.

Does the 554BM000159DGR support LVDS output, and what are its electrical characteristics?

Yes, the 554BM000159DGR uses LVDS output with a nominal common-mode voltage of 1.20 V, differential swing of 0.7 VPP (typical), and 45–55% duty cycle symmetry. It requires 100 Ω differential termination and operates within 10–945 MHz range. The 554BM000159DGR meets LVDS electrical standards with <350 ps rise/fall times and supports 155.52 MHz operation with 0.37 ps RMS phase jitter (12 kHz–20 MHz).

What is the tuning slope (KV) and absolute pull range (APR) of the 554BM000159DGR?

The 554BM000159DGR has a tuning slope (KV) of 90 ppm/V and delivers ±30 ppm absolute pull range (APR) at 3.3 V supply. This is calculated as 0.5 × 3.3 V × 90 ppm/V − 50 ppm (temp stability) − 10 ppm (aging), meeting telecom-grade APR requirements. The VC input accepts 0–3.3 V with 500 kΩ input impedance and 10.0 kHz modulation bandwidth.

How is frequency selection implemented on the 554BM000159DGR?

Frequency selection on the 554BM000159DGR is performed using two digital inputs: FS[1] (pin 7) and FS[0] (pin 8). These pins decode four states (00, 01, 10, 11) to select the corresponding preprogrammed frequency. The selection is latched internally and takes ≤20 ms to settle. Both pins include 17 kΩ internal pull-up resistors to VDD, simplifying interface design.

Is the 554BM000159DGR RoHS-compliant and qualified for industrial temperature operation?

Yes, the 554BM000159DGR is Pb-free/RoHS-compliant (marked with '+' on top) and qualified for continuous operation from –40 °C to +85 °C ambient temperature. It meets MIL-STD-883F mechanical shock/vibration, J-STD-020 MSL 1 moisture sensitivity, and JEDEC J-STD-020C soldering profiles - making it suitable for industrial, telecom, and outdoor base station applications.

554BM000159DGR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si554

Package/Case:: 8-SMD, No Lead

Packaging:: Tape & Reel (TR)

Product Status:: Active

Base Resonator:: Crystal

Type:: VCXO

Frequency - Output 1:: 74.175824MHz, 74.25MHz, 148.35165MHz, 148.5MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVDS

Voltage - Supply:: 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 108mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

554BM000159DGR FAQ

1.How can I place an order for 554BM000159DGR through Aetrix?

Please submit a Request for Quotation (RFQ) for 554BM000159DGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 554BM000159DGR reliable?

The price and inventory of 554BM000159DGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 554BM000159DGR is usually 5 days.

3.What payment methods are accepted for 554BM000159DGR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 554BM000159DGR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 554BM000159DGR?

554BM000159DGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 554BM000159DGR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 554BM000159DGR?

For technical support, including 554BM000159DGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 554BM000159DGR requirements.

6.How does Aetrix verify that 554BM000159DGR is sourced from the original manufacturer or authorized distributors?

All 554BM000159DGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 554BM000159DGR meets industry standards.

7.What is the process for return or replacement of 554BM000159DGR?

All 554BM000159DGR units undergo pre-shipment inspection (PSI). If there is an issue with 554BM000159DGR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 554BM000159DGR part is unused and in its original packaging.

Return procedure for 554BM000159DGR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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