Skyworks Solutions Inc. 554KD000129DG

Overview

554KD000129DG from Skyworks Solutions is a quad-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed output frequencies of 125 MHz, 155.52 MHz, 156.25 MHz, and 161.1328125 MHz; supports 3.3 V supply, LVPECL output, ±50 ppm temperature stability, 90 ppm/V tuning slope, and operates from –40 to +85 °C in telecom clock recovery and 10GbE line cards.

For engineers reviewing the 554KD000129DG datasheet, 554KD000129DG pinout, 554KD000129DG application, or 554KD000129DG equivalent, this page delivers verified electrical specs, DSPLL®-based jitter performance (0.26–0.32 ps RMS), frequency select logic, VC control interface behavior, and real-world timing use cases in optical transport and SONET/SDH systems.

Technical Context

The 554KD000129DG implements Skyworks' third-generation DSPLL® architecture with a fixed internal crystal reference, enabling four user-selectable output frequencies via FS[1:0] inputs without external loop filters or VCOs. It integrates on-chip tuning slope calibration and supports active-high OE with internal 17 kΩ pull-up to VDD.

Its VC input accepts 0–VDD control voltage with nominal VCNOM = VDD/2, delivering ±100 ppm absolute pull range at 90 ppm/V slope; phase jitter is specified across OC-48 (12 kHz–20 MHz) and OC-192 (50 kHz–80 MHz) integration bands, with worst-case 0.32 ps RMS for >500 MHz outputs.

Key Specifications

Pinout & Package

554KD000129DG is housed in an industry-standard 5 × 7 mm, 8-pad surface-mount package (RoHS-compliant, Pb-free), compatible with IPC-7351 land patterns and reflow soldering per JEDEC J-STD-020C.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-frequency VCXO applications.

Compared with Si552KD000129DG and 554AF000124DGR, the 554KD000129DG uniquely delivers four telecom-aligned frequencies below 200 MHz with optimal 90 ppm/V KV for jitter-sensitive 10GbE and OTN applications - balancing APR headroom and phase noise performance better than either alternative.

Availability

554KD000129DG is available at Aetrix Electronics and suitable for SONET/SDH line cards, 10GbE PHY modules, optical transport equipment, and clock and data recovery circuits requiring stable component supply with full traceability and lifecycle management.

Supply support for 554KD000129DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and precision analog products for infrastructure and mobile markets.

The Si554 product line delivers programmable, low-jitter VCXOs for carrier-grade timing applications including synchronous optical networking, high-speed Ethernet, and optical transport - designed to replace legacy SAW and discrete PLL-based oscillators with single-chip reliability.

FAQ

What are the four factory-programmed output frequencies of the 554KD000129DG?

The 554KD000129DG is configured with four specific output frequencies: 125 MHz, 155.52 MHz, 156.25 MHz, and 161.1328125 MHz. These are permanently programmed at Skyworks' factory and selected via the FS[1:0] pins. The 554KD000129DG does not support user-defined frequencies outside this set, and all timing specifications - including phase jitter and stability - are validated at these exact rates.

Does the 554KD000129DG support CMOS output format?

No, the 554KD000129DG does not support CMOS output. Its part number suffix 'K' indicates LVPECL output with 3.3 V supply and active-high OE polarity. CMOS is only available in Si554 variants with suffixes C, G, J, P, T, or V - and even then, limited to ≤160 MHz. The 554KD000129DG's LVPECL outputs require 50 Ω termination to VDD–2.0 V for proper signal integrity.

What is the Absolute Pull Range (APR) of the 554KD000129DG, and how is it calculated?

The 554KD000129DG has an Absolute Pull Range of ±100 ppm, derived from its 90 ppm/V tuning slope and 3.3 V supply: APR = 0.5 × VDD × KV – stability – aging = 0.5 × 3.3 × 90 – 50 – 10 = ±100 ppm. This value is confirmed in Table 3 of the datasheet and represents the maximum frequency deviation achievable over temperature, aging, and supply variation - critical for PLL lock range validation.

How does the DSPLL® architecture in the 554KD000129DG improve jitter performance compared to traditional VCXOs?

The 554KD000129DG's DSPLL® architecture uses a fixed internal crystal reference and digital synthesis to generate output frequencies, eliminating the phase noise and aging sensitivity of voltage-tuned SAW resonators. This yields 0.26 ps RMS phase jitter (12 kHz–20 MHz), up to 3× lower than comparable SAW-based VCXOs, and provides superior supply noise rejection - directly measurable in noisy SERDES card environments where the 554KD000129DG maintains jitter compliance.

Can the 554KD000129DG operate at 2.5 V or 1.8 V supply voltage?

No, the 554KD000129DG is specified exclusively for 3.3 V operation, as indicated by the 'K' in its part number (per Section 3 "Ordering Information"). Supply voltage options of 2.5 V and 1.8 V are assigned to different suffixes (e.g., 'E', 'F', 'G' for 2.5 V; 'J', 'K', 'V', 'W' for 1.8 V). Applying 2.5 V or 1.8 V to the 554KD000129DG will result in undefined behavior, failure to meet jitter or stability specs, and potential damage per Absolute Maximum Ratings.