Skyworks Solutions Inc. 564AAEA002110ABGR

Overview

564AAEA002110ABGR from Skyworks Solutions is an I²C-programmable ultra-low-jitter crystal oscillator (XO) delivering user-defined frequencies from 0.2 to 3000 MHz with <1 ppb resolution, 90 fs RMS phase jitter (12 kHz–20 MHz), ±50 ppm total stability over –40 to +85 °C, and support for LVPECL/LVDS/CML/HCSL/CMOS/Dual CMOS output formats in a 5×7 mm CLCC package - deployed in 100G/400G optical Ethernet and FPGA clocking systems.

For engineers reviewing the 564AAEA002110ABGR datasheet, 564AAEA002110ABGR pinout, 564AAEA002110ABGR application, or 564AAEA002110ABGR equivalent, this page delivers verified electrical specs, factory-configured startup behavior, I²C reprogramming capability, PSNR (–80 dBc typ), and dual-voltage operation (1.8/2.5/3.3 V) critical for high-speed serial interface timing design.

Technical Context

The 564AAEA002110ABGR implements Skyworks' 4th-generation DSPLL® architecture with a fixed 152.6 MHz crystal reference, fractional feedback divider (FBDIV, 11.32-bit), high-speed integer divider (HSDIV, 4–2046), and power-of-2 low-speed divider (LSDIV, 1–32), enabling glitchless frequency synthesis across its full range. Its digital loop filter and on-chip power supply regulation provide deterministic jitter performance independent of integer/fractional output selection.

Factory-programmed configuration includes startup frequency, I²C address, output format (LVPECL), OE pin polarity/location, and voltage rail (3.3 V). The device supports 100 kbps/400 kbps/1 Mbps I²C Fast Mode Plus, with settling time of 100 µs for small frequency changes (<±950 ppm) and 40 ms for large transitions (including VCO recalibration).

Key Specifications

Pinout & Package

564AAEA002110ABGR is housed in a hermetically sealed 5×7 mm 8-pin CLCC package with gold-plated contact pads (Au/Ni), MSL Level 1, and JEDEC J-STD-020-compliant solder profile (260 °C peak, 20–40 s).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Compared with Si569ACB002110ABG and Si549BA002110AGM, the 564AAEA002110ABGR uniquely combines 3000 MHz capability, I²C agility, and triple-voltage operation - making it the sole option for next-gen 400G+ optical systems requiring both bandwidth headroom and runtime configurability.

Availability

564AAEA002110ABGR is available at Aetrix Electronics and suitable for 100G/400G optical Ethernet, FPGA/ASIC clocking, and broadcast video applications requiring stable component supply, rapid prototyping cycles, and long-term production continuity.

Supply support for 564AAEA002110ABGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad manufacturing scale and reliability certification.

The Si564 Ultra Series™ is engineered for high-speed digital systems demanding ultra-low jitter, field-programmable frequency agility, and robust supply noise immunity - targeting optical networking, datacenter switching, and broadcast video infrastructure.

FAQ

What output frequency range does the 564AAEA002110ABGR support?

The 564AAEA002110ABGR supports 0.2 to 3000 MHz for LVPECL, LVDS, and CML outputs; 0.2 to 400 MHz for HCSL; and 0.2 to 250 MHz for CMOS and Dual CMOS formats. This range covers 10G/40G/100G/400G Ethernet, OTN, SDI, and FPGA reference clocks. Frequency selection is performed via I²C commands with <1 ppb resolution, and the device is factory-configured for LVPECL output at shipment.

Does the 564AAEA002110ABGR require external programming hardware?

No - the 564AAEA002110ABGR is fully functional upon power-up using its factory-programmed startup frequency and I²C address. External programming hardware is optional: I²C commands from an MCU or host processor can dynamically reconfigure frequency, output enable behavior, or format without interrupting operation. Skyworks provides free software tools (e.g., ClockBuilder Pro) to generate register values and validate configurations before deployment.

What is the phase jitter performance of the 564AAEA002110ABGR at 156.25 MHz?

At 156.25 MHz LVPECL output, the 564AAEA002110ABGR delivers 95 fs RMS phase jitter (12 kHz–20 MHz), as specified in Table 2.3 of the datasheet. This value is measured under standard conditions (VDD = 3.3 V, TA = 25 °C) and remains within 140 fs maximum across temperature and voltage. It meets stringent requirements for 10G/25G Ethernet PHYs and SONET OC-192 interfaces.

Can the 564AAEA002110ABGR operate from a 1.8 V supply?

Yes - the 564AAEA002110ABGR operates from 1.8 V, 2.5 V, or 3.3 V supplies (±5%) with identical jitter and stability specifications. All output formats (LVPECL, LVDS, CMOS, etc.) and I²C functionality are supported across all three rails. No hardware modification or configuration change is required when switching supply voltages; the device auto-detects VDD level and adjusts driver bias accordingly.

How does the 564AAEA002110ABGR handle power supply noise?

The 564AAEA002110ABGR integrates on-chip power supply filtering that achieves –80 dBc typical power supply noise rejection (PSNR) across 100 kHz–1 MHz. When tested with 50 mV_PP ripple at 1 MHz, spurs induced in the 156.25 MHz LVDS output are suppressed to –85 dBc. This eliminates the need for external LDOs or ferrite beads in noisy switch-mode power supply domains, simplifying layout and reducing BOM count.