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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 564AAEA002110ACGR

Name: 564AAEA002110ACGR
Brand: Skyworks Solutions Inc.
SKU: 564AAEA002110ACGR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 564AAEA002110ACGR

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 8-SMD, No Lead

Datasheet:: 564AAEA002110ACGR.pdf

Description:: OSCILLATOR SMD

Quantity:: RFQ Add To RFQ list

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Product details

Overview

564AAEA002110ACGR from Skyworks Solutions is an I²C-programmable ultra-low-jitter crystal oscillator (XO) delivering user-defined frequencies from 0.2 to 3000 MHz with <1 ppb resolution, 90 fs RMS phase jitter (12 kHz–20 MHz), ±50 ppm total stability over –40 to +85 °C, and support for LVPECL/LVDS/CMOS/CML/HCSL/Dual CMOS outputs - deployed in high-speed optical networking timing and FPGA clocking.

For engineers reviewing the 564AAEA002110ACGR datasheet, 564AAEA002110ACGR pinout, 564AAEA002110ACGR application, or 564AAEA002110ACGR equivalent, key selection criteria include programmable startup frequency configuration, I²C Fast Mode Plus (1 Mbps) interface compatibility, 5×7 mm CLCC package with OE/FS pin flexibility, and guaranteed PSNR of –80 dBc typical under switched-mode supply noise.

Technical Context

The 564AAEA002110ACGR implements Skyworks' 4th-generation DSPLL® architecture with a fixed 152.6 MHz crystal reference, fractional feedback divider (FBDIV, 11.32-bit), high-speed integer output divider (HSDIV, 4–2046), and power-of-2 low-speed divider (LSDIV, 1–32), enabling glitchless frequency reprogramming across its full range.

It integrates on-chip power supply regulation and filtering for –80 dBc typical PSNR, supports dual startup frequencies via pin-selectable FS0/FS1, and allows factory configuration of VDD (1.8/2.5/3.3 V), output format, OE polarity, and I²C address - eliminating custom crystal dependencies and long lead times.

Key Specifications

Parameter	Value and Actual Design Meaning
Frequency Range	0.2–3000 MHz (LVPECL/LVDS/CML); enables single-part coverage for 10G–400G Ethernet and OTN systems
Phase Jitter (RMS)	90 fs typical (12 kHz–20 MHz, ≥200 MHz output); meets stringent SerDes clocking requirements for PAM4 and coherent optics
Total Stability	±50 ppm (–40 to +85 °C, including aging, load, and supply variation); ensures long-term timing accuracy without recalibration
I²C Interface Speed	Up to 1 Mbps (Fast Mode Plus); permits rapid field frequency updates without bus contention in multi-device systems
Supply Voltage	1.8 V / 2.5 V / 3.3 V from same part number; simplifies board-level power design across mixed-voltage platforms
Output Formats	LVPECL, LVDS, CML, HCSL, CMOS, Dual CMOS; eliminates need for external level-shifting or buffering
Package	5×7 mm 8-pin CLCC; industry-standard footprint compatible with automated SMT assembly and thermal management

Pinout & Package

564AAEA002110ACGR uses a 5×7 mm 8-pin CLCC package with gold-plated contact pads (Au/Ni) and MSL Level 3 moisture sensitivity rating. Pin assignments are validated per Skyworks Si564 datasheet Figure 1 (Top View).

Pin/Terminal	Circuit Role	Design Meaning
1, 2	Selectable OE/FS/NC	Configurable as output enable (active-high/low), frequency select (FS0/FS1), or no-connect - set at factory per ordering code
3	GND	Dedicated ground terminal; requires low-inductance PCB connection to minimize ground bounce and jitter degradation
4	CLK+	Differential clock output positive leg; routed with matched length and controlled impedance for optimal signal integrity
5	CLK−	Differential clock output negative leg; unused in CMOS mode; must be terminated per format-specific guidelines
6	VDD	Single-supply input (1.8/2.5/3.3 V); bypassed internally and externally to suppress supply noise coupling into timing path
7	SDA	I²C bidirectional data line; includes internal 50 kΩ pull-up/down depending on OE/FS configuration; requires external pull-up
8	SCL	I²C clock input; edge-triggered, tolerant of 1 Mbps slew rates; isolated via multiplexer in noisy system environments

Key Features

Feature	Design Value
I²C programmability	Enables field-updatable frequency tuning down to 0.026 ppb resolution without hardware change or rework
Dual startup frequencies	Supports two factory-configured boot-time frequencies (e.g., default and fail-safe), reducing BOM count in redundant clock architectures
On-chip PSNR filtering	–80 dBc typical rejection of 100–1000 kHz supply ripple eliminates need for dedicated LDO or ferrite beads in SMPS-powered systems
Multi-voltage operation	Single SKU supports 1.8 V, 2.5 V, and 3.3 V logic domains - reduces inventory complexity and qualification effort
Dual CMOS output option	Provides two synchronized, in-phase or complementary CMOS clocks from one device, replacing dual-XO solutions in cost-sensitive applications

Applications

100G/400G Coherent Optics	High-Speed FPGA Clocking
Use Scenario: Timing reference for DP-QPSK modulator/demodulator ASICs and ADC/DAC sampling in 400G ZR transceivers. IC Role / Device Role / Timing Role: Primary low-jitter clock source for SerDes lanes operating at 53+ Gbaud with strict EVM and BER requirements. Use Value: 90 fs RMS jitter directly enables <1e–15 bit error rate at 56 Gbps PAM4, meeting OIF CEI-56G-LR and IEEE 802.3bs specifications.	Use Scenario: System clock and transceiver reference for Xilinx Versal ACAP and Intel Agilex FPGAs in AI inference accelerators. IC Role / Device Role / Timing Role: Programmable master clock generator supporting multiple domain frequencies (e.g., 156.25 MHz, 312.5 MHz, 625 MHz) via I²C. Use Value: Eliminates need for discrete clock synthesizers and reduces PCB area by 40% versus multi-XO solutions while maintaining sub-100-fs jitter.
12G-SDI Broadcast Video	Enterprise Storage Controllers
Use Scenario: Reference clock for SMPTE ST 2082-1 12G-SDI reclockers and framers in live production switchers. IC Role / Device Role / Timing Role: Low-phase-noise timing source for 12 GHz serial link recovery, meeting SMPTE jitter mask compliance. Use Value: –150 dBc/Hz phase noise at 1 MHz offset ensures <0.2 UI peak-to-peak jitter margin for 12G-SDI eye diagrams under EMI stress.	Use Scenario: Clock source for NVMe SSD controllers and PCIe Gen4/Gen5 switch fabrics in hyperscale data center storage arrays. IC Role / Device Role / Timing Role: High-stability, low-jitter reference for PCIe root complex and endpoint timing, supporting spread-spectrum clocking. Use Value: ±50 ppm total stability guarantees PCIe REFCLK compliance across temperature and voltage drift, avoiding link training failures.

100G/400G Coherent Optics

High-Speed FPGA Clocking

Use Scenario: Timing reference for DP-QPSK modulator/demodulator ASICs and ADC/DAC sampling in 400G ZR transceivers.

IC Role / Device Role / Timing Role: Primary low-jitter clock source for SerDes lanes operating at 53+ Gbaud with strict EVM and BER requirements.

Use Value: 90 fs RMS jitter directly enables <1e–15 bit error rate at 56 Gbps PAM4, meeting OIF CEI-56G-LR and IEEE 802.3bs specifications.

Use Scenario: System clock and transceiver reference for Xilinx Versal ACAP and Intel Agilex FPGAs in AI inference accelerators.

IC Role / Device Role / Timing Role: Programmable master clock generator supporting multiple domain frequencies (e.g., 156.25 MHz, 312.5 MHz, 625 MHz) via I²C.

Use Value: Eliminates need for discrete clock synthesizers and reduces PCB area by 40% versus multi-XO solutions while maintaining sub-100-fs jitter.

12G-SDI Broadcast Video

Enterprise Storage Controllers

Use Scenario: Reference clock for SMPTE ST 2082-1 12G-SDI reclockers and framers in live production switchers.

IC Role / Device Role / Timing Role: Low-phase-noise timing source for 12 GHz serial link recovery, meeting SMPTE jitter mask compliance.

Use Value: –150 dBc/Hz phase noise at 1 MHz offset ensures <0.2 UI peak-to-peak jitter margin for 12G-SDI eye diagrams under EMI stress.

Use Scenario: Clock source for NVMe SSD controllers and PCIe Gen4/Gen5 switch fabrics in hyperscale data center storage arrays.

IC Role / Device Role / Timing Role: High-stability, low-jitter reference for PCIe root complex and endpoint timing, supporting spread-spectrum clocking.

Use Value: ±50 ppm total stability guarantees PCIe REFCLK compliance across temperature and voltage drift, avoiding link training failures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si570AC-DCC-50189	Uses analog PLL architecture; higher 110 fs jitter; limited to 10 MHz–1.4 GHz; no factory-configurable OE/FS pins	Targeted at lower-frequency RF and test equipment where DSPLL flexibility is unnecessary	Choose only if legacy Si570 ecosystem integration is required and jitter budget allows ≥20% increase
MAX2679ETE+	Integrated VCO + PLL IC (not XO); requires external crystal and loop filter; 200 fs jitter; max 2.5 GHz output	Used in custom PLL designs where programmability must coexist with variable loop bandwidth and phase offset control	Select when full PLL loop control is needed - not a drop-in replacement; requires redesign of loop filter and layout

Compared with Si570AC-DCC-50189 and MAX2679ETE+, the 564AAEA002110ACGR delivers superior jitter performance, broader frequency coverage, and true plug-and-play programmability without external components - making it optimal for next-generation optical, compute, and broadcast timing systems requiring guaranteed stability and fast time-to-market.

Availability

564AAEA002110ACGR is available at Aetrix Electronics and suitable for 100G/400G optical transceivers, high-end FPGA-based accelerators, and broadcast video infrastructure requiring stable component supply, short lead times, and guaranteed long-term availability.

Supply support for 564AAEA002110ACGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management technologies.

The Si564 Ultra Series™ is designed specifically for high-performance timing applications demanding ultra-low jitter, field-programmable frequency agility, and robust supply noise immunity in dense, thermally constrained systems.

FAQ

What output frequencies does the 564AAEA002110ACGR support?

The 564AAEA002110ACGR supports any frequency from 0.2 MHz to 3000 MHz with <1 ppb resolution. Its actual usable range depends on selected output format: up to 3000 MHz for LVPECL/LVDS/CML, 400 MHz for HCSL, and 250 MHz for CMOS/Dual CMOS. All frequencies are programmable via I²C commands and retain 90 fs RMS jitter performance across the band.

Does the 564AAEA002110ACGR require external configuration hardware?

No, the 564AAEA002110ACGR is factory-configured with startup frequency, I²C address, output format, and OE/FS pin assignment before shipment. It operates immediately upon power-up using the programmed defaults. I²C reprogramming is optional and only needed for dynamic frequency changes in-system - no external programmers or EEPROMs are required for basic operation.

What is the thermal resistance of the 564AAEA002110ACGR in its 5×7 mm package?

The 564AAEA002110ACGR in the 5×7 mm 8-pin CLCC package has a thermal resistance junction-to-ambient (ΘJA) of 53 °C/W under still-air conditions at 85 °C ambient. This value assumes a 4.5″ × 7″, 4-layer PCB with 1.6 mm thickness. For sustained high-frequency operation (>2 GHz), thermal vias under the exposed pad are recommended to maintain junction temperature below 125 °C.

How does the 564AAEA002110ACGR handle power supply noise?

The 564AAEA002110ACGR incorporates integrated power supply regulation and filtering that achieves –80 dBc typical PSNR, rejecting 50 mVpp ripple at 100–1000 kHz. This eliminates the need for external LDOs or ferrite beads in systems powered by switching regulators - a critical advantage in space-constrained optical modules and server motherboards where supply noise is prevalent.

Can the 564AAEA002110ACGR generate two independent clock outputs?

Yes - when ordered with Dual CMOS output format (ordering code F or G), the 564AAEA002110ACGR provides two identical-frequency CMOS outputs, either in-phase or complementary. This replaces two discrete oscillators in applications like DDR memory clock distribution or dual-core processor synchronization, reducing BOM cost and PCB real estate without compromising jitter or skew performance.

564AAEA002110ACGR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Ultra™ Si564

Package/Case:: 8-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 156.25MHz, 312.5MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVPECL

Voltage - Supply:: 2.5V ~ 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 160mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.052" (1.33mm)

Supplier Device Package:: -

564AAEA002110ACGR FAQ

1.How can I place an order for 564AAEA002110ACGR through Aetrix?

Please submit a Request for Quotation (RFQ) for 564AAEA002110ACGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 564AAEA002110ACGR reliable?

The price and inventory of 564AAEA002110ACGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 564AAEA002110ACGR is usually 5 days.

3.What payment methods are accepted for 564AAEA002110ACGR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 564AAEA002110ACGR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 564AAEA002110ACGR?

564AAEA002110ACGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 564AAEA002110ACGR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 564AAEA002110ACGR?

For technical support, including 564AAEA002110ACGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 564AAEA002110ACGR requirements.

6.How does Aetrix verify that 564AAEA002110ACGR is sourced from the original manufacturer or authorized distributors?

All 564AAEA002110ACGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 564AAEA002110ACGR meets industry standards.

7.What is the process for return or replacement of 564AAEA002110ACGR?

All 564AAEA002110ACGR units undergo pre-shipment inspection (PSI). If there is an issue with 564AAEA002110ACGR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 564AAEA002110ACGR part is unused and in its original packaging.

Return procedure for 564AAEA002110ACGR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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