Skyworks Solutions Inc. 564AAGA002110ABGR

Overview

564AAGA002110ABGR from Skyworks Solutions is an I²C-programmable ultra-low-jitter crystal oscillator (XO) delivering user-defined frequencies from 0.2 to 3000 MHz with <1 ppb resolution. It features 90 fs RMS phase jitter (12 kHz–20 MHz), ±50 ppm total frequency stability over –40 to +85 °C, and supports LVPECL/LVDS/CML/HCSL/CMOS/Dual CMOS output formats in a 5×7 mm CLCC package. It serves as a programmable clock source for high-speed optical networking and FPGA/ASIC timing.

For engineers reviewing the 564AAGA002110ABGR datasheet, 564AAGA002110ABGR pinout, 564AAGA002110ABGR application, or 564AAGA002110ABGR equivalent, this device enables rapid custom-frequency prototyping (1–2 week samples), eliminates crystal-bin dependency, and provides guaranteed PSNR of –80 dBc while supporting multi-voltage operation (1.8/2.5/3.3 V) and flexible startup configuration via pin-selectable OE/FS options.

Technical Context

The 564AAGA002110ABGR implements Skyworks' 4th-generation DSPLL® architecture with a fixed 152.6 MHz crystal reference, fractional feedback divider (FBDIV, 11.32-bit), and cascaded HSDIV (integer, 4–2046) and LSDIV (power-of-2, 1–32) output dividers. Its digital loop filter and on-chip power supply regulation enable stable synthesis across integer and fractional frequencies without external components.

It integrates factory-programmed startup settings-including initial frequency, I²C address, output format, and OE/FS pin polarity-while retaining full runtime reprogrammability via 100 kbps/400 kbps/1 Mbps I²C. The device uses internal NVM to retain configuration and supports glitchless small-step frequency changes (<±950 ppm) within 100 µs.

Key Specifications

Pinout & Package

564AAGA002110ABGR is housed in a hermetically sealed 5×7 mm 8-pin CLCC package with gold-plated contact pads (Au/Ni). Pin 1 is marked by a dot; top-view orientation follows standard CLCC convention.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Compared with Si570AC-DCC1B025 and MAX2680AUB+T, the 564AAGA002110ABGR delivers superior jitter performance, wider frequency coverage, and true field-programmability - making it the only option suitable for next-generation optical interconnects and adaptive compute platforms.

Availability

564AAGA002110ABGR is available at Aetrix Electronics and suitable for 100G/400G optical networking, FPGA-based acceleration, and high-precision test equipment requiring stable component supply, rapid sampling, and long-term lifecycle continuity.

Supply support for 564AAGA002110ABGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in semiconductor innovation, specializing in analog and mixed-signal technologies for wireless, infrastructure, and timing markets.

The Si564 family was engineered to replace fixed-frequency crystal oscillators with a single, software-defined timing solution - targeting high-speed communications, datacenter, and test instrumentation where frequency agility, ultra-low jitter, and supply-chain agility are critical.

FAQ

What output formats does the 564AAGA002110ABGR support?

The 564AAGA002110ABGR supports LVPECL, LVDS, CML, HCSL, CMOS, and Dual CMOS (in-phase or complementary) output formats. The specific format is factory-programmed at shipment and cannot be changed in-circuit. Output drive strength and termination requirements vary by format - refer to Figures 4.1–4.3 in the Si564 datasheet for recommended AC/DC coupling networks and resistor values per VDD rail.

Does the 564AAGA002110ABGR require external configuration after power-up?

No. The 564AAGA002110ABGR ships with factory-programmed startup frequency, I²C address, OE/FS pin assignment, and output format. It begins operating immediately upon power-up at its configured startup frequency. I²C reprogramming is optional and used only for dynamic frequency changes during operation - no boot-time initialization sequence is needed.

What is the maximum frequency supported by the 564AAGA002110ABGR in CMOS mode?

The 564AAGA002110ABGR supports up to 250 MHz in CMOS or Dual CMOS output mode, as specified in Table 2.1 of the Si564 datasheet. This limit applies regardless of VDD voltage (1.8/2.5/3.3 V) and is enforced by internal driver design to maintain 45–55% duty cycle and <1.5 ns rise/fall times under 5 pF load.

How does the 564AAGA002110ABGR achieve ultra-low jitter despite using a fixed crystal?

The 564AAGA002110ABGR uses Skyworks' 4th-generation DSPLL® technology: a fixed 152.6 MHz crystal feeds a digitally controlled oscillator (DCO) and fractional-N synthesizer. Phase noise from the crystal is suppressed by the digital loop filter, while the DCO's high-frequency operation (10.8–13.1 GHz) and optimized divider chain minimize quantization noise - achieving 90 fs RMS jitter without analog VCO drift or temperature sensitivity.

Can the 564AAGA002110ABGR be used with a 1.8 V supply while driving LVPECL outputs?

No. LVPECL output operation requires VDD = 2.5 V or 3.3 V, as stated in Table 2.1. At 1.8 V, only LVDS, CML, HCSL, CMOS, and Dual CMOS outputs are supported. Attempting LVPECL operation at 1.8 V will result in invalid common-mode voltage and undefined swing - potentially causing signal integrity failure or receiver lock loss.