Skyworks Solutions Inc. 564AAJA002119ABGR

Overview

564AAJA002119ABGR from Skyworks Solutions is an I²C-programmable ultra-low-jitter crystal oscillator (XO) delivering 90 fs RMS phase jitter (12 kHz–20 MHz), programmable from 0.2 to 3000 MHz with <1 ppb resolution, and factory-configured for LVPECL output, 3.3 V supply, ±50 ppm total stability, and 5×7 mm CLCC package. It serves as a high-precision clock source in 100G/400G optical transport and FPGA/ASIC timing systems.

For engineers reviewing the 564AAJA002119ABGR datasheet, 564AAJA002119ABGR pinout, 564AAJA002119ABGR application, or 564AAJA002119ABGR equivalent, key selection criteria include its DSPLL-based frequency agility, guaranteed aging performance over 20 years, PSNR of –80 dBc typical, and support for pin-selectable startup frequencies without external components.

Technical Context

The 564AAJA002119ABGR implements Skyworks' 4th-generation DSPLL architecture with a fixed 152.6 MHz crystal reference, fractional feedback divider (FBDIV, 11.32-bit), integer high-speed divider (HSDIV, 4–2046), and power-of-2 low-speed divider (LSDIV, 1–32). Its digital loop filter and on-chip power supply regulation enable stable synthesis across integer and fractional output frequencies.

It supports I²C Fast Mode Plus (1 Mbps), offers configurable OE/FS pin polarity and location, and integrates NVM to store startup configuration. Output enable time is ≤20 µs and power-up time is ≤10 ms, with tristate Hi-Z current of 73 mA.

Key Specifications

Pinout & Package

564AAJA002119ABGR is housed in a hermetically sealed 5×7 mm 8-pin CLCC package with gold-plated contact pads (Au/Ni) and moisture sensitivity level (MSL) 1. Pin 1 is GND; pins 4 and 5 deliver complementary LVPECL outputs; pins 7 and 8 are I²C SDA/SCL; pin 2 is configured as OE (active-high, pin 1 location per ordering code A).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Compared with 564AAJA002119ABGR, Si569AC000119AGM trades package size and output format for slightly lower power and identical jitter performance, while Si549BA000119AGM prioritizes stability and miniaturization at the cost of maximum frequency and jitter floor - making 564AAJA002119ABGR optimal for high-speed optical and FPGA applications requiring >300 MHz and <100 fs jitter.

Availability

564AAJA002119ABGR is available at Aetrix Electronics and suitable for 100G/400G optical modules, high-end FPGA/ASIC platforms, and broadcast video equipment requiring stable component supply, short lead times, and guaranteed long-term availability.

Supply support for 564AAJA002119ABGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad manufacturing scale and reliability validation.

The Si564 Ultra Series is designed for high-performance timing applications demanding ultra-low jitter, field-programmable frequency agility, and robust operation in noisy power environments - targeting optical networking, datacenter switching, and high-speed serial interfaces.

FAQ

What is the guaranteed phase jitter performance of the 564AAJA002119ABGR across its full frequency range?

The 564AAJA002119ABGR guarantees 90 fs RMS phase jitter (12 kHz–20 MHz) for output frequencies ≥200 MHz, 105 fs for 100–200 MHz, and 200 fs for CMOS outputs between 10–250 MHz. These values are characterized and specified in Table 2.3 of the official Skyworks datasheet and apply under standard conditions (VDD = 3.3 V ±5%, TA = –40 to 85 °C, no active I²C traffic). The 564AAJA002119ABGR achieves this using DSPLL architecture with on-chip power supply noise rejection.

Can the 564AAJA002119ABGR be reprogrammed in-system, and what are the I²C timing requirements?

Yes, the 564AAJA002119ABGR supports full in-system frequency reprogramming via I²C at speeds up to 1 Mbps (Fast Mode Plus). SDA and SCL inputs require VIH ≥0.7×VDD and VIL ≤0.3×VDD. Settling time is ≤100 µs for small frequency changes (<±950 ppm) and ≤40 ms for large changes (>±950 ppm), including internal VCO calibration. The 564AAJA002119ABGR retains its last programmed frequency in nonvolatile memory after power cycle.

What is the meaning of the ordering code '564AAJA002119ABGR' and how does it map to physical configuration?

The ordering code 564AAJA002119ABGR decodes as: Si564 series (564), temperature grade A (–40 to +85 °C), total stability A (±50 ppm), output format A (LVPECL), VDD option A (2.5/3.3 V), package A (5×7 mm), revision G, tape-and-reel packaging (R). The 'J' indicates I²C programmability; '002119' is the custom frequency code placeholder; 'AB' denotes OE pin location (pin 1) and polarity (active-high). This exact configuration is factory-programmed before shipment.

Does the 564AAJA002119ABGR support multiple startup frequencies, and how are they selected?

Yes, the 564AAJA002119ABGR supports up to four user-defined startup frequencies stored in NVM. Selection is performed via dedicated FS0/FS1 pins (not present on this variant - pin 2 is OE, pin 6 is NC), or via I²C command at power-up. For 564AAJA002119ABGR specifically, the default startup frequency is factory-programmed; pin-based frequency select is disabled per ordering code A (OE on pin 1, no FS pins assigned). All frequency changes post-power-up require I²C access.

What thermal and reliability specifications apply to the 564AAJA002119ABGR in continuous operation?

The 564AAJA002119ABGR has a maximum junction temperature of 125 °C and operates continuously from –40 to +85 °C ambient. Its 5×7 mm CLCC package exhibits ΘJA = 53 °C/W (still air). Reliability is validated per MIL-STD-883 methods for shock, vibration, solderability, and leak testing. Aging is guaranteed at ±50 ppm over 20 years at 70 °C, and the device meets JEDEC J-STD-020 for reflow (260 °C peak, 20–40 sec). The 564AAJA002119ABGR also features 2 kV HBM ESD protection.