Skyworks Solutions Inc. 564AAJA002160ABGR

Overview

564AAJA002160ABGR from Skyworks Solutions is an I²C-programmable ultra-low-jitter crystal oscillator (XO) delivering user-defined frequencies from 0.2 to 3000 MHz with <1 ppb resolution. It features 90 fs RMS phase jitter (12 kHz–20 MHz), ±50 ppm total frequency stability over –40 to +85 °C, and supports LVPECL/LVDS/CML/HCSL/CMOS/Dual CMOS output formats in a 5×7 mm CLCC package. It serves as a programmable clock source for high-speed optical networking and FPGA timing.

For engineers reviewing the 564AAJA002160ABGR datasheet, 564AAJA002160ABGR pinout, 564AAJA002160ABGR application, or 564AAJA002160ABGR equivalent, this device enables rapid custom-frequency deployment without crystal change-critical for 100G/400G OTN, coherent optics, and high-density server clock trees where jitter, supply noise immunity, and multi-format flexibility are design-critical.

Technical Context

The 564AAJA002160ABGR implements Skyworks' 4th-generation DSPLL® architecture with a fixed 152.6 MHz crystal reference and fractional-N feedback divider (FBDIV, 11.32-bit format), high-speed integer divider (HSDIV, 4–2046), and power-of-2 low-speed divider (LSDIV, 1–32). This enables glitchless frequency reprogramming across its full range.

It integrates on-chip power supply regulation and >–80 dBc PSNR, allowing stable operation under switched-mode supply noise. Startup frequency, I²C address, OE polarity, and pin-selectable frequency select (FS0/FS1) are factory-configured per order-no field programming required for baseline operation.

Key Specifications

Pinout & Package

564AAJA002160ABGR is housed in a hermetically sealed 5×7 mm 8-pin CLCC package with gold-plated contact pads (Au/Ni), MSL Level 1, and JEDEC-compliant reflow profile (260 °C peak).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Compared with Si569AC000113AGM and Si549BB000111DG, the 564AAJA002160ABGR offers broader frequency coverage (0.2–3000 MHz), lowest jitter (90 fs), and full I²C configurability-making it optimal for high-performance, multi-standard systems where flexibility and signal integrity are non-negotiable.

Availability

564AAJA002160ABGR is available at Aetrix Electronics and suitable for 100G/400G optical networking, high-density server clock trees, and FPGA-based prototyping platforms requiring stable component supply, fast sampling, and long-term lifecycle continuity.

Supply support for 564AAJA002160ABGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, timing, and precision analog components for communications, automotive, and industrial markets.

The Si564 Ultra Series™ is engineered for high-speed digital systems demanding ultra-low jitter, field-programmable frequency agility, and robust supply noise rejection-targeting next-gen optical transport, AI accelerators, and real-time video infrastructure.

FAQ

What output frequency ranges does the 564AAJA002160ABGR support?

The 564AAJA002160ABGR supports 0.2 to 3000 MHz for LVPECL, LVDS, and CML outputs; 0.2 to 400 MHz for HCSL; and 0.2 to 250 MHz for CMOS and Dual CMOS formats. These ranges are guaranteed across its full operating temperature (–40 to +85 °C) and supply voltage (1.8/2.5/3.3 V) specifications per Skyworks' Si564 datasheet Rev. 206621A.

Does the 564AAJA002160ABGR require external configuration after soldering?

No-the 564AAJA002160ABGR ships with factory-programmed startup frequency, I²C address, output format, and OE/FS pin configuration. I²C reprogramming is optional and only needed if dynamic frequency changes are required during system operation; default behavior is immediate clock output at power-up.

What is the phase jitter performance of the 564AAJA002160ABGR at 156.25 MHz?

At 156.25 MHz LVPECL output, the 564AAJA002160ABGR delivers 95 fs RMS phase jitter (12 kHz–20 MHz), as specified in Table 2.3 of the Si564 datasheet. This meets OC-192/STM-64 SONET/SDH jitter limits and exceeds IEEE 802.3ba CAUI-4 requirements for 100G Ethernet.

Can the 564AAJA002160ABGR operate from a 1.8 V supply while driving LVPECL outputs?

Yes-the 564AAJA002160ABGR supports 1.8 V VDD operation with LVPECL output enabled. Its LVPECL driver is designed for 1.8/2.5/3.3 V rails; typical supply current is 110–160 mA, and output common-mode voltage shifts accordingly (e.g., V_OC ≈ VDD – 1.335 V at 1.8 V).

How does the 564AAJA002160ABGR achieve –80 dBc PSNR without external filtering?

The 564AAJA002160ABGR integrates on-die power supply regulation and proprietary noise-rejection circuitry that attenuates supply ripple across 100 kHz–1 MHz bands by >–80 dBc (typ.), as measured with 50 mV_pp sine-wave injection. This eliminates need for external LDOs or LC filters in most server and optical module designs.