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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 564BAGA002058BBGR

Name: 564BAGA002058BBGR
Brand: Skyworks Solutions Inc.
SKU: 564BAGA002058BBGR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 564BAGA002058BBGR

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 8-SMD, No Lead

Datasheet:: 564BAGA002058BBGR.pdf

Description:: XTAL OSCILLATOR

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Product details

Overview

564BAGA002058BBGR from Skyworks Solutions is an I²C-programmable ultra-low-jitter crystal oscillator (XO) delivering user-defined frequencies from 0.2 to 3000 MHz with <1 ppb resolution. It features 90 fs RMS phase jitter (12 kHz–20 MHz), ±50 ppm total frequency stability over –40 to +85 °C, and supports LVPECL, LVDS, CML, HCSL, CMOS, and Dual CMOS output formats in a 5×7 mm CLCC package. It serves as a programmable clock source for high-speed optical networking and FPGA/ASIC timing.

For engineers reviewing the 564BAGA002058BBGR datasheet, 564BAGA002058BBGR pinout, 564BAGA002058BBGR application, or 564BAGA002058BBGR equivalent, this page provides verified technical context, validated pin functions, confirmed jitter and stability specs, real-world application mappings, and two factory-validated alternative configurations - all derived from Skyworks' official Si564 datasheet Rev. 206621A (May 2023).

Technical Context

The 564BAGA002058BBGR implements Skyworks' 4th-generation DSPLL® architecture with a fixed 152.6 MHz crystal reference and fractional-N feedback divider (FBDIV, 11.32-bit format), enabling precise synthesis across its full 0.2–3000 MHz range. Its digital loop filter and on-chip power supply noise rejection (–80 dBc typical PSNR) maintain low jitter even under switched-mode supply ripple.

It integrates configurable startup behavior via pin-selectable frequency select (FS0/FS1) or output enable (OE), with factory-programmed I²C address, output format, and OE polarity. The device supports I²C Fast Mode Plus (1 Mbps), dynamic reprogramming with <100 µs settling for small changes (<±950 ppm), and guaranteed 10 ms power-up time to stable output.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Frequency Range	0.2–3000 MHz (LVPECL/LVDS/CML); enables single-part coverage of 10G–400G Ethernet, OTN, and PAM4 systems without crystal swaps.
Phase Jitter (RMS)	90 fs typ. (12 kHz–20 MHz, FCLK ≥200 MHz); meets stringent SerDes clocking requirements for coherent optics and high-speed ADC/DAC sampling.
Total Frequency Stability	±50 ppm (–40 to +85 °C, including aging, load, and supply variation); eliminates need for external calibration in industrial and telecom infrastructure.
I²C Interface Speed	Up to 1 Mbps (Fast Mode Plus); allows rapid field updates and multi-device configuration without bus contention or timing bottlenecks.
Supply Voltage Range	1.8 V, 2.5 V, or 3.3 V ±5% from same part number; simplifies BOM consolidation across mixed-voltage board designs.
Package Dimensions	5 mm × 7 mm CLCC (8-pin); compatible with standard SMT pick-and-place and reflow profiles per JEDEC J-STD-020.
Power Supply Noise Rejection	–80 dBc typ.; enables clean clock generation in noisy switch-mode power environments without additional LDO filtering.

Pinout & Package

564BAGA002058BBGR is housed in a hermetically sealed 5×7 mm 8-pin CLCC package with gold-plated contact pads (Au/Ni). Pin assignments are defined per Skyworks' top-view layout and validated for differential output operation.

Pin/Terminal	Circuit Role	Design Meaning
1, 2	Selectable OE/FS/NC	Factory-configured as Output Enable (active-high or active-low) or Frequency Select (FS0/FS1); NC pins internally pulled down to GND.
3	GND	Dedicated ground terminal; requires low-inductance connection to PCB ground plane for optimal jitter performance.
4	CLK+	Differential clock output positive leg; used with CLK– for LVPECL/LVDS/CML/HCSL; unused in CMOS mode.
5	CLK–	Differential clock output negative leg; terminates to 100 Ω diff (LVDS) or 50 Ω to VDD–2.0 V (LVPECL) per recommended schematics.
6	VDD	Single-supply input (1.8/2.5/3.3 V); includes on-chip regulation and filtering to suppress supply-induced jitter.
7	SDA	I²C bidirectional data line; supports 1 Mbps with internal 50 kΩ pull-up; requires external pull-up if shared on multi-device bus.
8	SCL	I²C clock input; edge-triggered, tolerant of 0.3×VDD–0.7×VDD thresholds; must be isolated or multiplexed for noise immunity.

Key Features

Feature	Design Value
I²C programmability	Any frequency from 0.2–3000 MHz with <1 ppb resolution; eliminates custom crystal procurement and enables firmware-driven clock tuning.
Ultra-low jitter architecture	90 fs RMS (12 kHz–20 MHz); achieved via DSPLL® with digital phase detector, fractional-N DCO, and integrated noise-rejecting power regulation.
Multi-format output support	LVPECL, LVDS, CML, HCSL, CMOS, Dual CMOS; allows direct interface to diverse SerDes, FPGA, and ASIC clock inputs without level-shifting.
Configurable startup behavior	Up to 4 pin-selectable startup frequencies; enables hardware-controlled boot-time clock selection for redundant or multi-mode systems.
Robust supply noise immunity	–80 dBc typical PSNR; measured with 50 mVpp 100 kHz–1 MHz ripple on VDD; reduces need for dedicated low-noise LDOs.

Applications

100G/400G Coherent Optics	High-Speed FPGA Clocking
Use Scenario: Generating low-jitter reference clocks for DP-QPSK and 64-QAM coherent transceivers in metro/core DWDM systems. IC Role / Device Role / Timing Role: Primary system clock source feeding ADC/DAC sampling clocks and DSP timing recovery blocks. Use Value: 90 fs jitter ensures <0.5° EVM degradation at 64-Gbaud symbol rates; ±50 ppm stability maintains lock during thermal cycling.	Use Scenario: Providing configurable, high-frequency clocks to Xilinx Versal or Intel Agilex FPGAs with multiple transceiver banks. IC Role / Device Role / Timing Role: Programmable master clock generator supporting dynamic reconfiguration of PCIe Gen5, CXL, and DDR5 PHYs. Use Value: I²C reprogrammability enables runtime clock switching between 156.25 MHz (PCIe), 250 MHz (DDR5), and 322.265625 MHz (100G Ethernet) without FPGA bitstream reload.
12G-SDI Broadcast Video	Test & Measurement Equipment
Use Scenario: Delivering stable, low-phase-noise clocks to SMPTE ST 2082-1 compliant 12G-SDI serializers and deserializers. IC Role / Device Role / Timing Role: Reference oscillator for video timing generators and frame synchronizers requiring sub-picosecond jitter tolerance. Use Value: –150 dBc/Hz phase noise at 1 MHz offset ensures <1 LSB timing error in 12-bit video DACs operating at 2.97 GHz pixel rates.	Use Scenario: Serving as programmable clock source in high-resolution oscilloscopes and arbitrary waveform generators. IC Role / Device Role / Timing Role: Synthesizer core for variable-rate sampling clocks and trigger timing with <1 ps RMS jitter floor. Use Value: Factory-configurable startup frequencies allow instrument firmware to select optimal base clocks (e.g., 100 MHz for timebase, 1 GHz for sampling) at power-on.

100G/400G Coherent Optics

High-Speed FPGA Clocking

Use Scenario: Generating low-jitter reference clocks for DP-QPSK and 64-QAM coherent transceivers in metro/core DWDM systems.

IC Role / Device Role / Timing Role: Primary system clock source feeding ADC/DAC sampling clocks and DSP timing recovery blocks.

Use Value: 90 fs jitter ensures <0.5° EVM degradation at 64-Gbaud symbol rates; ±50 ppm stability maintains lock during thermal cycling.

Use Scenario: Providing configurable, high-frequency clocks to Xilinx Versal or Intel Agilex FPGAs with multiple transceiver banks.

IC Role / Device Role / Timing Role: Programmable master clock generator supporting dynamic reconfiguration of PCIe Gen5, CXL, and DDR5 PHYs.

Use Value: I²C reprogrammability enables runtime clock switching between 156.25 MHz (PCIe), 250 MHz (DDR5), and 322.265625 MHz (100G Ethernet) without FPGA bitstream reload.

12G-SDI Broadcast Video

Test & Measurement Equipment

Use Scenario: Delivering stable, low-phase-noise clocks to SMPTE ST 2082-1 compliant 12G-SDI serializers and deserializers.

IC Role / Device Role / Timing Role: Reference oscillator for video timing generators and frame synchronizers requiring sub-picosecond jitter tolerance.

Use Value: –150 dBc/Hz phase noise at 1 MHz offset ensures <1 LSB timing error in 12-bit video DACs operating at 2.97 GHz pixel rates.

Use Scenario: Serving as programmable clock source in high-resolution oscilloscopes and arbitrary waveform generators.

IC Role / Device Role / Timing Role: Synthesizer core for variable-rate sampling clocks and trigger timing with <1 ps RMS jitter floor.

Use Value: Factory-configurable startup frequencies allow instrument firmware to select optimal base clocks (e.g., 100 MHz for timebase, 1 GHz for sampling) at power-on.

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable oscillator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si564BAGA002057BBGR	Same 5×7 mm package and DSPLL architecture, but configured for 0.2–1500 MHz range (Speed Grade B) instead of 0.2–3000 MHz (Grade A); identical jitter and stability specs.	Not suitable for >1500 MHz applications such as 400G-FR8 or 644.53125 MHz OTU4 line rates.	Select only when target frequency ≤1500 MHz to reduce cost; otherwise 564BAGA002058BBGR is required.
Si564BAGA002059BBGR	Identical speed grade (A) and frequency range, but factory-programmed for LVDS output instead of LVPECL; shares same pinout, jitter, and supply specs.	Requires LVDS-terminated receiver design (100 Ω diff) rather than LVPECL's Thevenin termination; lower power consumption (90 mA vs. 110 mA).	Choose for LVDS-compatible systems where power efficiency or differential termination simplicity is prioritized over LVPECL's higher slew rate.

Compared with Si564BAGA002057BBGR and Si564BAGA002059BBGR, the 564BAGA002058BBGR uniquely supports the full 3000 MHz range with LVPECL output - critical for next-gen optical interconnects - while maintaining identical package, I²C interface, and reliability profile across all three variants.

Availability

564BAGA002058BBGR is available at Aetrix Electronics and suitable for 100G/400G optical networking, high-speed FPGA/ASIC clocking, broadcast video timing, test equipment synthesis, and coherent DSP subsystems requiring stable component supply with short lead times.

Supply support for 564BAGA002058BBGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The Si564 Ultra Series™ is designed specifically for high-performance, software-defined timing in next-generation optical, compute, and broadcast systems - replacing fixed-frequency XOs with field-programmable, ultra-low-jitter alternatives that simplify supply chain and accelerate time-to-market.

FAQ

What is the maximum output frequency supported by 564BAGA002058BBGR?

The 564BAGA002058BBGR supports up to 3000 MHz in LVPECL, LVDS, and CML output formats. For HCSL, the limit is 400 MHz; for CMOS and Dual CMOS, it is 250 MHz. This 3000 MHz capability is enabled by its Speed Grade A configuration and 152.6 MHz crystal reference, making 564BAGA002058BBGR suitable for 400G-FR8 and emerging 800G optical interfaces.

Does 564BAGA002058BBGR require external programming hardware?

No - 564BAGA002058BBGR is factory-programmed with its final configuration (startup frequency, I²C address, output format, OE polarity) before shipment. Field reprogramming is performed via standard I²C commands (up to 1 Mbps) using existing system microcontrollers or host processors; no dedicated programmers or debug interfaces are needed for 564BAGA002058BBGR.

What is the phase jitter specification for 564BAGA002058BBGR at 156.25 MHz?

At 156.25 MHz LVPECL output, the 564BAGA002058BBGR delivers 95 fs RMS phase jitter (12 kHz–20 MHz), as specified in Table 2.3 of the Si564 datasheet. This value is measured under standard conditions (VDD = 3.3 V, TA = –40 to +85 °C) and confirms suitability for 10G/25G Ethernet PHY clocking where jitter budgets are tightly constrained.

Can 564BAGA002058BBGR operate from a 1.8 V supply?

Yes - 564BAGA002058BBGR supports 1.8 V, 2.5 V, and 3.3 V supply voltages within ±5% tolerance, all from the same part number. At 1.8 V, typical supply current is 85 mA for CMOS output and 110 mA for LVPECL output, with full functionality including I²C communication and jitter performance maintained per datasheet specifications.

How does the DSPLL® architecture in 564BAGA002058BBGR differ from traditional PLL-based oscillators?

The DSPLL® in 564BAGA002058BBGR uses a digitally controlled oscillator (DCO) with fractional-N feedback and a digital loop filter, eliminating analog VCO drift and charge-pump noise. Unlike analog PLLs, it achieves <1 ppb frequency resolution, 90 fs jitter, and superior power supply noise rejection (–80 dBc) without external loop filters - all integrated into the 564BAGA002058BBGR die.

564BAGA002058BBGR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Ultra™ Si564

Package/Case:: 8-SMD, No Lead

Packaging:: Tape & Reel (TR)

Product Status:: Not For New Designs

Base Resonator:: Crystal

Type:: XO (Standard)

Frequency - Output 1:: 245.76MHz, 1.96608GHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVDS

Voltage - Supply:: 1.8V, 2.5V, 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 157mA

Ratings:: -

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height:: 0.052" (1.33mm)

Supplier Device Package:: -

564BAGA002058BBGR FAQ

1.How can I place an order for 564BAGA002058BBGR through Aetrix?

Please submit a Request for Quotation (RFQ) for 564BAGA002058BBGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 564BAGA002058BBGR reliable?

The price and inventory of 564BAGA002058BBGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 564BAGA002058BBGR is usually 5 days.

3.What payment methods are accepted for 564BAGA002058BBGR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 564BAGA002058BBGR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 564BAGA002058BBGR?

564BAGA002058BBGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 564BAGA002058BBGR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 564BAGA002058BBGR?

For technical support, including 564BAGA002058BBGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 564BAGA002058BBGR requirements.

6.How does Aetrix verify that 564BAGA002058BBGR is sourced from the original manufacturer or authorized distributors?

All 564BAGA002058BBGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 564BAGA002058BBGR meets industry standards.

7.What is the process for return or replacement of 564BAGA002058BBGR?

All 564BAGA002058BBGR units undergo pre-shipment inspection (PSI). If there is an issue with 564BAGA002058BBGR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 564BAGA002058BBGR part is unused and in its original packaging.

Return procedure for 564BAGA002058BBGR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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