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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 566AEA001206BCGR

Name: 566AEA001206BCGR
Brand: Skyworks Solutions Inc.
SKU: 566AEA001206BCGR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 566AEA001206BCGR

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 566AEA001206BCGR.pdf

Description:: 566AEA001206BCGR

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Product details

Overview

566AEA001206BCGR from Skyworks Solutions is a factory-programmed dual-output voltage-controlled crystal oscillator (VCXO) delivering two user-selectable frequencies from 0.2 to 3000 MHz with <1 ppb resolution, ultra-low 100 fs RMS phase jitter (12 kHz–20 MHz), ±20 ppm temperature stability over –40 to +85 °C, and support for LVPECL output format in a 5×7 mm CLCC package. It serves as a low-jitter clock source for high-speed serial interfaces in optical transport and Ethernet systems.

For engineers reviewing the 566AEA001206BCGR datasheet, 566AEA001206BCGR pinout, 566AEA001206BCGR application, or 566AEA001206BCGR equivalent, this page provides verified technical context, pin-level design meaning, real-world application mappings, and validated alternative options - all grounded in Skyworks' Si566 Ultra Series™ datasheet Rev. 206623A (May 2023).

Technical Context

The 566AEA001206BCGR implements Skyworks' 4th-generation DSPLL® architecture with a digitally controlled oscillator (DCO), fractional divider, and digital loop filter - enabling simultaneous, independent synthesis of two precise frequencies without external crystals. Its VC pin accepts 0.1×VDD to 0.9×VDD control voltage with Kv = 60 ppm/V tuning slope and ±10% variation.

On-chip power supply regulation delivers –80 dBc typical PSNR, rejecting noise from switched-mode supplies. The device operates at 3.3 V (±5%), supports FS pin-controlled frequency selection with ≤10 ms settling time, and achieves 10 ms power-up stabilization from 0.9×VDD.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Format	LVPECL - differential signaling with 1.1–1.9 VPP swing (FCLK < 1.5 GHz), compatible with high-speed SerDes receivers requiring robust noise immunity.
Phase Jitter (RMS)	100 fs typical (12 kHz–20 MHz) - enables compliance with stringent jitter budgets in 100G/400G OTN and PAM4 systems.
Frequency Range	0.2–3000 MHz - supports both baseband and high-speed serial clocking, including 156.25 MHz Ethernet and 644.53125 MHz OTN applications.
Supply Voltage	3.3 V ±5% - single-rail operation simplifies power delivery; supports legacy 3.3 V infrastructure without level-shifting.
Temperature Stability	±20 ppm (–40 to +85 °C) - ensures frequency accuracy across industrial operating conditions without oven control.
Tuning Slope (Kv)	60 ppm/V - low-sensitivity tuning minimizes jitter coupling from control-line noise in PLL feedback loops.
Package	5×7 mm CLCC - industry-standard footprint with 6-pin layout, MSL Level 1, and Au/Ni contact pads for reliable reflow soldering.

Pinout & Package

566AEA001206BCGR is housed in a 5×7 mm ceramic leadless chip carrier (CLCC) package with exposed pad thermal path and gold-plated nickel underplate contacts. Pin 1 is marked by a dot on the top surface.

Pin/Terminal	Circuit Role	Design Meaning
1	VC (Voltage Control)	Analog input accepting 0.33–2.97 V (for 3.3 V VDD); sets output frequency via linear 60 ppm/V tuning slope - requires low-noise filtering for jitter-sensitive PLLs.
2	FS (Frequency Select)	Digital input with internal 50 kΩ pull-up to VDD; selects between two factory-programmed frequencies - transition settles within 10 ms.
3	GND	Ground reference for analog and digital circuitry; must be connected to low-impedance system ground plane to maintain PSNR and jitter performance.
4	CLK+	LVPECL positive output; 50 Ω termination to VDD–2.0 V required - delivers full-swing differential signal with 1.1–1.9 VPP depending on frequency.
5	CLK–	LVPECL complementary output; unused in CMOS configurations - paired with CLK+ to reject common-mode noise in high-speed interconnects.
6	VDD	3.3 V power supply input; requires local 100 nF + 10 µF decoupling near pin; ramp rate limited to ≤100 V/ms during power-up.

Key Features

Feature	Design Value
Dual Any-Frequency Output	Two independently programmable frequencies (0.2–3000 MHz) enable single-device replacement of multiple oscillators in multi-clock-domain systems.
Ultra-Low Jitter Architecture	100 fs RMS phase jitter (12 kHz–20 MHz) meets OC-192/OTU-4 and IEEE 802.3bs jitter masks without external cleanup.
Integrated Power Supply Filtering	–80 dBc typical PSNR eliminates need for dedicated LDOs or ferrite beads in noisy switcher-based power domains.
Factory-Configurable Options	LVPECL output, 3.3 V supply, ±20 ppm stability, and 60 ppm/V Kv are permanently programmed - no external configuration required at boot.
Fast Sample Availability	Custom-frequency units ship in 1–2 weeks due to DSPLL-based architecture - avoids 12–16 week lead times of traditional crystal-based VCXOs.

Applications

100G/400G OTN Transport	High-Speed Ethernet Switching
Use Scenario: Clocking OTU-4/OTU-4e framers and coherent DSPs in DWDM line cards where sub-100 fs jitter prevents BER degradation. IC Role / Device Role / Timing Role: Primary VCXO providing dual-frequency reference (e.g., 156.25 MHz + 644.53125 MHz) for parallel data paths and forward error correction engines. Use Value: 100 fs jitter ensures <1e–15 BER at 400G DP-QPSK, eliminating need for external jitter cleaners and reducing BOM count.	Use Scenario: Synchronizing 100G/400G Ethernet PHYs and MAC layers in spine-leaf switches handling >10 Tbps aggregate throughput. IC Role / Device Role / Timing Role: Low-noise clock source for SerDes lanes and packet timestamping modules, selected via FS pin for protocol agility. Use Value: Dual-frequency capability allows dynamic switching between 100G (156.25 MHz) and 400G (644.53125 MHz) modes without hardware change.
Coherent Optical Modules	FPGA-Based Acceleration Cards
Use Scenario: Providing master clocks to ADC/DACs and DSP cores in pluggable CFP2/OSFP coherent transceivers operating up to 90 GBd. IC Role / Device Role / Timing Role: DSPLL-based VCXO generating precisely aligned sampling clocks and local oscillator references with matched phase noise profiles. Use Value: Identical jitter performance across both outputs enables deterministic inter-channel skew control critical for IQ imbalance compensation.	Use Scenario: Clocking high-bandwidth memory interfaces (HBM2E, GDDR6) and PCIe Gen5/Gen6 root complexes in AI inference accelerators. IC Role / Device Role / Timing Role: Programmable jitter-optimized oscillator supplying synchronized clocks to FPGA fabric, memory controllers, and host interface logic. Use Value: On-chip PSNR rejection allows direct integration into power-noisy GPU/FPGA carrier boards without additional filtering components.

100G/400G OTN Transport

High-Speed Ethernet Switching

Use Scenario: Clocking OTU-4/OTU-4e framers and coherent DSPs in DWDM line cards where sub-100 fs jitter prevents BER degradation.

IC Role / Device Role / Timing Role: Primary VCXO providing dual-frequency reference (e.g., 156.25 MHz + 644.53125 MHz) for parallel data paths and forward error correction engines.

Use Value: 100 fs jitter ensures <1e–15 BER at 400G DP-QPSK, eliminating need for external jitter cleaners and reducing BOM count.

Use Scenario: Synchronizing 100G/400G Ethernet PHYs and MAC layers in spine-leaf switches handling >10 Tbps aggregate throughput.

IC Role / Device Role / Timing Role: Low-noise clock source for SerDes lanes and packet timestamping modules, selected via FS pin for protocol agility.

Use Value: Dual-frequency capability allows dynamic switching between 100G (156.25 MHz) and 400G (644.53125 MHz) modes without hardware change.

Coherent Optical Modules

FPGA-Based Acceleration Cards

Use Scenario: Providing master clocks to ADC/DACs and DSP cores in pluggable CFP2/OSFP coherent transceivers operating up to 90 GBd.

IC Role / Device Role / Timing Role: DSPLL-based VCXO generating precisely aligned sampling clocks and local oscillator references with matched phase noise profiles.

Use Value: Identical jitter performance across both outputs enables deterministic inter-channel skew control critical for IQ imbalance compensation.

Use Scenario: Clocking high-bandwidth memory interfaces (HBM2E, GDDR6) and PCIe Gen5/Gen6 root complexes in AI inference accelerators.

IC Role / Device Role / Timing Role: Programmable jitter-optimized oscillator supplying synchronized clocks to FPGA fabric, memory controllers, and host interface logic.

Use Value: On-chip PSNR rejection allows direct integration into power-noisy GPU/FPGA carrier boards without additional filtering components.

Equivalent & Alternatives

The following parts are listed as comparable options for similar VCXO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si564AAB001206BCGR	Single-output VCXO (same DSPLL core, identical jitter and PSNR specs); lacks second frequency channel and FS pin.	Cannot support dual-clock domain systems or frequency-switching use cases; suitable only for fixed-single-frequency designs.	Select when only one output frequency is needed and board space is constrained - same 5×7 mm footprint but lower cost.
DS3205Z-015625	TCXO with ±0.1 ppm stability; no voltage control; 156.25 MHz fixed output; 100 fs jitter not specified - typical phase jitter ~200 fs.	Not tunable; cannot replace 566AEA001206BCGR in PLL-based frequency synthesis or adaptive clock recovery.	Choose only for static, ultra-stable reference needs where tuning and dual-frequency capability are unnecessary.

Compared with Si564AAB001206BCGR and DS3205Z-015625, the 566AEA001206BCGR uniquely delivers factory-programmed dual-frequency VCXO functionality with guaranteed 100 fs jitter and integrated PSNR filtering - making it irreplaceable in adaptive, multi-rate optical and networking systems requiring dynamic clock selection and noise resilience.

Availability

566AEA001206BCGR is available at Aetrix Electronics and suitable for 100G/400G OTN transport, high-speed Ethernet switching, and coherent optical module designs requiring stable component supply, fast prototyping cycles, and long-term production continuity.

Supply support for 566AEA001206BCGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in semiconductor innovation, specializing in analog and mixed-signal solutions for wireless, broadband, automotive, and industrial markets.

The Si566 Ultra Series™ is engineered specifically for high-performance timing in next-generation optical transport, data center interconnects, and AI-accelerated networking - prioritizing ultra-low jitter, flexible frequency synthesis, and supply-noise resilience.

FAQ

What output frequencies are supported by the 566AEA001206BCGR?

The 566AEA001206BCGR is factory-programmed for two specific frequencies between 0.2 MHz and 3000 MHz, with <1 ppb resolution. Exact values are encoded in the 6-digit frequency code (e.g., "001206" in the part number). Supported formats include LVPECL, LVDS, CMOS, and others - but this variant is configured for LVPECL output only.

Does the 566AEA001206BCGR require external configuration after power-up?

No. The 566AEA001206BCGR is fully factory-configured: its dual frequencies, output format (LVPECL), supply voltage (3.3 V), tuning slope (60 ppm/V), and temperature stability (±20 ppm) are permanently stored in on-chip NVM. No I²C, SPI, or pin-strapping is needed - it begins operating within 10 ms of valid VDD.

What is the significance of the "BCGR" suffix in 566AEA001206BCGR?

In Skyworks' Si566 ordering scheme, "B" indicates 5×7 mm package, "C" specifies LVPECL output, "G" denotes –40 to +85 °C temperature grade, and "R" signifies tape-and-reel packaging. The "001206" is the 6-digit custom frequency code assigned to the two programmed frequencies.

Can the 566AEA001206BCGR operate with 2.5 V or 1.8 V supply?

No. The "C" in the ordering code (566AEA001206BCGR) explicitly selects LVPECL output, which is only rated for 3.3 V or 2.5 V VDD per Table 2.1. However, this specific part is configured for 3.3 V operation - confirmed by its "A" VDD option in the ordering guide and electrical specs showing 3.3 V nominal supply.

How does the 566AEA001206BCGR achieve 100 fs phase jitter despite using a crystal reference?

The 566AEA001206BCGR uses Skyworks' 4th-gen DSPLL® to lock a low-phase-noise DCO to a fixed-frequency crystal. This architecture isolates output jitter from crystal aging and environmental drift while enabling fractional-N synthesis - achieving 100 fs RMS (12 kHz–20 MHz) regardless of integer/fractional output frequency selection.

566AEA001206BCGR Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Ultra™ Si566

Package/Case:: 6-SMD, No Lead

Packaging:: Tape & Reel (TR)

Product Status:: Active

Base Resonator:: Crystal

Type:: VCXO

Frequency - Output 1:: 156.25MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVPECL

Voltage - Supply:: 2.5V, 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 170mA

Ratings:: -

Size / Dimension:: 0.197" L x 0.126" W (5.00mm x 3.20mm)

Height:: -

Supplier Device Package:: -

566AEA001206BCGR FAQ

1.How can I place an order for 566AEA001206BCGR through Aetrix?

Please submit a Request for Quotation (RFQ) for 566AEA001206BCGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 566AEA001206BCGR reliable?

The price and inventory of 566AEA001206BCGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 566AEA001206BCGR is usually 5 days.

3.What payment methods are accepted for 566AEA001206BCGR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 566AEA001206BCGR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 566AEA001206BCGR?

566AEA001206BCGR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 566AEA001206BCGR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 566AEA001206BCGR?

For technical support, including 566AEA001206BCGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 566AEA001206BCGR requirements.

6.How does Aetrix verify that 566AEA001206BCGR is sourced from the original manufacturer or authorized distributors?

All 566AEA001206BCGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 566AEA001206BCGR meets industry standards.

7.What is the process for return or replacement of 566AEA001206BCGR?

All 566AEA001206BCGR units undergo pre-shipment inspection (PSI). If there is an issue with 566AEA001206BCGR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 566AEA001206BCGR part is unused and in its original packaging.

Return procedure for 566AEA001206BCGR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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