Skyworks Solutions Inc. 566CFA000174ACGR

Overview

566CFA000174ACGR from Skyworks Solutions is a factory-programmed dual-frequency voltage-controlled crystal oscillator (VCXO) in a 5×7 mm CLCC package, delivering two user-selectable frequencies from 0.2 to 3000 MHz with <1 ppb resolution, ±20 ppm temperature stability over –40 to +85 °C, and ultra-low 100 fs RMS phase jitter (12 kHz–20 MHz) for high-speed serial data clocking in coherent optical modules.

For engineers reviewing the 566CFA000174ACGR datasheet, 566CFA000174ACGR pinout, 566CFA000174ACGR application, or 566CFA000174ACGR equivalent, this device supports LVPECL output, 3.3 V supply, dual CMOS buffer option, and frequency select (FS) control - critical for FPGA/ASIC clock domain management and 100G/400G OTN timing recovery systems.

Technical Context

The 566CFA000174ACGR implements Skyworks' 4th-generation DSPLL® architecture with fractional-N synthesis, enabling simultaneous low-jitter generation of two independent frequencies without external crystals. Its digital loop filter and on-chip DCO eliminate analog VCO drift while maintaining sub-100 fs jitter across integer and fractional frequencies.

On-die power supply regulation provides –80 dBc typical PSNR, rejecting noise from switched-mode supplies. The VC pin accepts 0.1×VDD to 0.9×VDD control voltage with Kv = 60 ppm/V tuning slope, and FS pin toggles between preprogrammed frequencies with ≤10 ms settling time.

Key Specifications

Pinout & Package

566CFA000174ACGR is housed in a 5×7 mm ceramic leadless chip carrier (CLCC) package with exposed pad ground connection and moisture sensitivity level (MSL) 1. Pin assignments are standardized across Si566 family variants.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar VCXO applications.

Compared with Si564A-A11583-GM and DS3205Z-156.25M, the 566CFA000174ACGR uniquely delivers dual-frequency agility, factory-programmable configuration, and lowest-in-class jitter - making it optimal for next-gen coherent optics and multi-rate SerDes systems where timing flexibility and signal integrity are co-dependent.

Availability

566CFA000174ACGR is available at Aetrix Electronics and suitable for 100G/400G optical modules, high-speed Ethernet switches, and FPGA-based test equipment requiring stable component supply, rapid prototyping turnaround, and long-term lifecycle continuity.

Supply support for 566CFA000174ACGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for infrastructure, automotive, and mobile markets.

The Si566 Ultra Series™ is designed specifically for high-performance timing applications demanding ultra-low jitter, dual-frequency flexibility, and simplified supply-chain logistics - targeting coherent optics, AI/ML accelerators, and next-generation data center interconnects.

FAQ

What output format and supply voltage does the 566CFA000174ACGR support?

The 566CFA000174ACGR is configured for LVPECL output and operates at 3.3 V ±5%. It draws up to 170 mA under full load and requires DC-coupled 50 Ω termination to VDD–2.0 V. This configuration is factory-programmed and cannot be changed in-circuit. The 566CFA000174ACGR supports differential signaling with 1.1–1.9 VPP swing depending on frequency, ensuring compatibility with high-speed SerDes receivers.

How is frequency selection implemented on the 566CFA000174ACGR?

The 566CFA000174ACGR uses a dedicated Frequency Select (FS) pin (Pin 2) to toggle between its two factory-programmed frequencies. When FS is logic-low, the first frequency is active; when FS is logic-high (internally pulled up to VDD), the second frequency is selected. Settling time after FS transition is ≤10 ms, and no external debounce or timing circuitry is required. The 566CFA000174ACGR stores both frequencies in on-chip NVM, eliminating boot-time configuration overhead.

What is the phase jitter performance of the 566CFA000174ACGR at 156.25 MHz?

At 156.25 MHz LVDS output with Kv = 60 ppm/V, the 566CFA000174ACGR delivers 110–130 fs RMS phase jitter (12 kHz–20 MHz). For LVPECL output at the same frequency, jitter is 100–150 fs RMS. These values are measured under standard conditions (VDD = 3.3 V, TA = 25 °C) and meet IEEE 802.3bj and OIF CEI-56G requirements. The 566CFA000174ACGR achieves this via DSPLL-based noise shaping and on-die power supply filtering.

Does the 566CFA000174ACGR require an external crystal or loop filter?

No. The 566CFA000174ACGR integrates a fixed-frequency crystal and fourth-generation DSPLL circuitry on-die, eliminating all external timing components. There is no need for an external crystal, loop filter capacitors, or varactor diodes. Configuration is stored in non-volatile memory, so the 566CFA000174ACGR powers up ready to operate with no initialization sequence - reducing system startup time and design complexity.

What package type and thermal characteristics apply to the 566CFA000174ACGR?

The 566CFA000174ACGR uses a 5×7 mm ceramic leadless chip carrier (CLCC) package with 6 terminals and MSL 1 rating. Its thermal resistance junction-to-ambient (ΘJA) is 53 °C/W under still-air conditions on a 4-layer PCB. Recommended layout includes two thermal vias under the exposed pad and tight decoupling (100 nF X7R + 10 µF tantalum) within 2 mm of VDD/GND pins to maintain jitter performance and reliability at full load.