Skyworks Solutions Inc. 566CFA000626ACGR

Overview

566CFA000626ACGR from Skyworks Solutions is a factory-programmed dual-frequency voltage-controlled crystal oscillator (VCXO) delivering two user-selectable output frequencies between 0.2 MHz and 3000 MHz with <1 ppb resolution, ultra-low 100 fs RMS phase jitter (12 kHz–20 MHz), ±20 ppm temperature stability over –40 to +85 °C, and LVPECL output format in a 5×7 mm CLCC package. It serves as a low-jitter clock source for high-speed serial interfaces requiring precise frequency agility.

For engineers reviewing the 566CFA000626ACGR datasheet, 566CFA000626ACGR pinout, 566CFA000626ACGR application, or 566CFA000626ACGR equivalent, key selection criteria include its dual-frequency VCXO architecture, DSPLL-based fractional synthesis, 60 ppm/V tuning slope (Kv), 3.3 V supply compatibility, and 5×7 mm footprint - all critical for coherent optics, PAM4, and high-end FPGA clocking designs where jitter, pull range, and layout space are constrained.

Technical Context

The 566CFA000626ACGR implements Skyworks' 4th-generation DSPLL® architecture with a digitally controlled oscillator (DCO), fractional divider, and digital loop filter, enabling independent synthesis of two integer/fractional frequencies without crystal swaps. Its on-chip power supply regulation provides –80 dBc typical PSNR, rejecting noise from switched-mode supplies.

Frequency selection is controlled via the FS pin (pin 2), while VC (pin 1) accepts 0.1×VDD to 0.9×VDD analog tuning voltage with ±10% Kv variation and 10 kHz modulation bandwidth. The device supports tristate output disable and achieves full frequency lock within 10 ms of power-up at ≤100 V/ms VDD ramp rate.

Key Specifications

Pinout & Package

566CFA000626ACGR is housed in a 5×7 mm ceramic leadless chip carrier (CLCC) package with exposed pad grounding and gold-plated nickel contacts. The package complies with JEDEC J-STD-020 reflow standards and features moisture sensitivity level (MSL) 1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Compared with Si564CFA000626ACGR and Si596CFA000626ACGR, the 566CFA000626ACGR offers the best trade-off of ultra-low jitter (100 fs), industrial temperature range, and rapid custom-frequency delivery in the largest 5×7 mm package - making it ideal for high-density switch fabric and test equipment where thermal dissipation and layout flexibility are prioritized over minimal footprint.

Availability

566CFA000626ACGR is available at Aetrix Electronics and suitable for 100G/400G coherent optics, 56G/112G PAM4 clocking, and FPGA/ASIC reference timing requiring stable component supply, guaranteed long-term availability, and traceable sourcing for production programs.

Supply support for 566CFA000626ACGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in analog and mixed-signal semiconductors, specializing in RF, mobile, infrastructure, and timing solutions with broad portfolio coverage and high-reliability manufacturing.

The Si566 Ultra Series™ VCXO product line was designed specifically for high-speed serial communication systems demanding ultra-low jitter, dual-frequency agility, and rapid customization - targeting next-generation optical transport, AI/ML hardware, and advanced test instrumentation.

FAQ

What is the factory-programmed frequency configuration for 566CFA000626ACGR?

The 566CFA000626ACGR is configured with two specific frequencies encoded in its six-digit frequency code "000626", which corresponds to 156.25 MHz and 312.5 MHz - standard rates for Ethernet and CPRI applications. These values are permanently stored in on-chip NVM and cannot be altered post-manufacture. The FS pin selects between them, and both frequencies maintain <100 fs jitter and ±20 ppm stability across temperature.

Does 566CFA000626ACGR support 1.8 V or 2.5 V supply operation?

Yes, the 566CFA000626ACGR supports 1.8 V, 2.5 V, and 3.3 V VDD operation from the same part number, but this specific variant is configured and tested for 3.3 V ±5%. When operated at 1.8 V or 2.5 V, supply current and output swing change per Table 2.1, and jitter increases slightly (e.g., +3 fs at 1.8 V). Always verify output compliance with receiver thresholds under actual VDD conditions.

How is the VC pin used to tune the output frequency of 566CFA000626ACGR?

The VC pin (pin 1) accepts an analog voltage from 0.33 V to 2.97 V (0.1× to 0.9× VDD) to adjust output frequency linearly with a tuning slope of 60 ppm/V. For example, applying 1.65 V to VC shifts each output frequency by ±100 ppm relative to nominal. Linearity is ±0.5%, and modulation bandwidth is 10 kHz - sufficient for slow-loop PLLs but not for high-speed spread-spectrum clocking.

What is the recommended termination for the LVPECL outputs of 566CFA000626ACGR?

For DC-coupled LVPECL operation, use Thevenin termination: 127 Ω from CLK+ to VDD and 82.5 Ω from CLK– to VDD (for 3.3 V supply). For AC-coupled operation, use 130 Ω pull-up on each output with 82.5 Ω and 127 Ω resistors forming a Thevenin network referenced to VDD – 2.0 V. Avoid unterminated or single-ended loads - mismatch causes reflections that degrade jitter and rise/fall times.

Can 566CFA000626ACGR replace two discrete VCXOs in a design?

Yes, the 566CFA000626ACGR is explicitly designed to replace two discrete VCXOs: its dual-frequency capability, shared DSPLL core, and single 5×7 mm footprint reduce component count, PCB area, and inter-device skew. Unlike two separate oscillators, it guarantees matched aging, temperature drift, and jitter profiles - critical for coherent sampling and multi-channel synchronization in test equipment and optical modules.