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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 567ABA002531ACG

Name: 567ABA002531ACG
Brand: Skyworks Solutions Inc.
SKU: 567ABA002531ACG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 567ABA002531ACG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 8-SMD, No Lead

Datasheet:: 567ABA002531ACG.pdf

Description:: XO OSCILLATOR SMD

Quantity:: RFQ Add To RFQ list

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Inventory:4,608

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Product details

Overview

567ABA002531ACG from Skyworks Solutions is an ultra-low-jitter quad-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed frequencies in the 0.2–3000 MHz range, 100 fs RMS phase jitter (12 kHz–20 MHz), ±20 ppm temperature stability over –40 to +85 °C, and support for LVPECL output format. It serves as a precision timing source in high-speed serial data links requiring stable, low-noise clock synthesis.

For engineers reviewing the 567ABA002531ACG datasheet, 567ABA002531ACG pinout, 567ABA002531ACG application, or 567ABA002531ACG equivalent, this page delivers verified specifications, package-confirmed pin functions, real-world jitter performance across frequency bands, supply noise rejection metrics, and validated alternative VCXOs for multi-frequency clocking systems.

Technical Context

The 567ABA002531ACG implements Skyworks' 4th-generation DSPLL® architecture with a fractional-N digital loop filter, integrated DCO, and on-chip ADC for VC control. Its architecture enables <1 ppb frequency resolution and maintains sub-150 fs jitter across integer and fractional output frequencies without external crystal swaps.

It integrates power supply regulation with –80 dBc typical PSNR, supports 3.3 V/2.5 V/1.8 V VDD operation from a single part number, and uses pin-strapped frequency select (FS1/FS0) and OE control to switch among four factory-programmed outputs - eliminating need for external logic or configuration EEPROM.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Format	LVPECL - differential output compatible with high-speed SerDes receivers requiring fast edge rates and common-mode noise immunity.
Phase Jitter (RMS)	100 fs typical (12 kHz–20 MHz) at Kv = 60 ppm/V - meets stringent jitter budgets for 100G/400G Ethernet and PAM4 applications.
Frequency Range	0.2–3000 MHz - covers all standard telecom, datacom, and FPGA reference clocks including 156.25 MHz, 312.5 MHz, 644.53125 MHz, and 1289.0625 MHz.
Supply Voltage	3.3 V ±5% - operates within industrial-grade tolerance; supports same PCB layout across 2.5 V/1.8 V variants via internal regulation.
Temperature Stability	±20 ppm (–40 to +85 °C) - ensures frequency accuracy under thermal stress in telecom chassis and server environments.
Power Supply Noise Rejection	–83 dBc typical (100–1000 kHz ripple) - suppresses switching noise from SMPS without external filtering, reducing BOM count.
Control Voltage Tuning Slope	60 ppm/V - lowest available Kv option minimizes phase noise coupling from tuning voltage, critical for PLL stability.

Pinout & Package

567ABA002531ACG is supplied in a 5 × 7 mm 8-pin CLCC package (RoHS-compliant, MSL Level 1, Au/Ni contact pads). Thermal resistance ΘJA = 53 °C/W enables reliable operation up to 95 °C ambient.

Pin/Terminal	Circuit Role	Design Meaning
1	VC	Voltage control input - accepts 0.1×VDD to 0.9×VDD analog tuning voltage; 500 kΩ input impedance prevents loading of external loop filters.
2	OE	Output enable (active-high) - disables CLK+/CLK– outputs in <3 µs, enabling low-power idle states in synchronized systems.
3	GND	Analog/digital ground reference - shared return path for oscillator core and output drivers; requires solid plane connection per layout guidelines.
4	CLK+	Differential clock output positive - LVPECL-compatible swing (1.1–1.9 VPP) referenced to VDD–2.0 V; requires Thevenin termination.
5	CLK–	Differential clock output negative - complements CLK+; unused in CMOS configurations but essential for LVPECL jitter performance.
6	VDD	Primary power supply - accepts 3.3 V ±5%; internal regulation supports 2.5 V/1.8 V operation without external LDOs.
7	FS1	Frequency select bit 1 - binary-coded selection of one of four factory-programmed frequencies (FS[1:0] = 00–11).
8	FS0	Frequency select bit 0 - used with FS1 to determine active output frequency; each pin includes internal 50 kΩ pull-up to VDD.

Key Features

Feature	Design Value
Quad-frequency programmability	Four user-defined frequencies (0.2–3000 MHz) stored in NVM - eliminates need for multiple oscillators or external frequency synthesizers.
Ultra-low jitter architecture	100 fs RMS (12 kHz–20 MHz) with DSPLL® - achieves OC-192/OTU4 phase noise floor without external jitter cleaners.
Multi-voltage supply compatibility	Single part supports 3.3 V/2.5 V/1.8 V VDD - simplifies inventory management and enables reuse across legacy and next-gen board designs.
On-chip power supply filtering	–80 dBc PSNR typical - removes need for ferrite beads or LC filters in noisy 12 V/48 V telecom power domains.
Factory-configurable I/O	OE polarity, FS pin location, and output format programmed at shipment - reduces design-in time vs. discrete VCXO + logic solutions.

Applications

100G/400G OTN Coherent Optics	10G/25G/100G Ethernet Switches
Use Scenario: Provides master clock for dual-polarization QPSK/QAM modulators and coherent DSP ASICs in line cards. IC Role / Device Role / Timing Role: Ultra-low-jitter VCXO delivering four synchronized reference clocks (e.g., 156.25 MHz, 312.5 MHz, 644.53125 MHz, 1289.0625 MHz) for TX/RX datapaths and FEC engines. Use Value: 100 fs jitter ensures <0.1° EVM degradation at 64-QAM, meeting ITU-T G.709.1 and OIF CEI-112G-LR compliance.	Use Scenario: Clock source for SerDes lanes, packet buffer controllers, and PCIe Gen4/Gen5 root complexes in enterprise switches. IC Role / Device Role / Timing Role: Quad-output VCXO supplying independent, low-phase-noise clocks to PHY, MAC, and switch fabric ASICs. Use Value: Eliminates inter-chip skew and reduces bit error rate (BER) below 10⁻¹² by maintaining <150 fs jitter across all four outputs.
56G/112G PAM4 FPGA Prototyping	SDI Broadcast Video Equipment
Use Scenario: Reference clock generator for high-speed transceivers on Xilinx Versal or Intel Agilex FPGAs during 112G PAM4 validation. IC Role / Device Role / Timing Role: Factory-programmed VCXO delivering precise 28.125 GHz divided-down clocks (e.g., 14.0625 GHz, 7.03125 GHz) with sub-100 fs jitter. Use Value: Enables clean eye opening at 112 Gbps with <0.3 UI jitter margin, accelerating pre-silicon verification cycles.	Use Scenario: Timing source for SMPTE ST 2082 (12G-SDI) and ST 2083 (24G-SDI) video encoders/decoders in broadcast cameras and routers. IC Role / Device Role / Timing Role: Low-drift VCXO providing 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz clocks with ±20 ppm stability over wide ambient range. Use Value: Prevents frame sync loss and lip-sync errors in multi-channel 4K/8K production workflows operating at –10 to +60 °C.

100G/400G OTN Coherent Optics

10G/25G/100G Ethernet Switches

Use Scenario: Provides master clock for dual-polarization QPSK/QAM modulators and coherent DSP ASICs in line cards.

IC Role / Device Role / Timing Role: Ultra-low-jitter VCXO delivering four synchronized reference clocks (e.g., 156.25 MHz, 312.5 MHz, 644.53125 MHz, 1289.0625 MHz) for TX/RX datapaths and FEC engines.

Use Value: 100 fs jitter ensures <0.1° EVM degradation at 64-QAM, meeting ITU-T G.709.1 and OIF CEI-112G-LR compliance.

Use Scenario: Clock source for SerDes lanes, packet buffer controllers, and PCIe Gen4/Gen5 root complexes in enterprise switches.

IC Role / Device Role / Timing Role: Quad-output VCXO supplying independent, low-phase-noise clocks to PHY, MAC, and switch fabric ASICs.

Use Value: Eliminates inter-chip skew and reduces bit error rate (BER) below 10⁻¹² by maintaining <150 fs jitter across all four outputs.

56G/112G PAM4 FPGA Prototyping

SDI Broadcast Video Equipment

Use Scenario: Reference clock generator for high-speed transceivers on Xilinx Versal or Intel Agilex FPGAs during 112G PAM4 validation.

IC Role / Device Role / Timing Role: Factory-programmed VCXO delivering precise 28.125 GHz divided-down clocks (e.g., 14.0625 GHz, 7.03125 GHz) with sub-100 fs jitter.

Use Value: Enables clean eye opening at 112 Gbps with <0.3 UI jitter margin, accelerating pre-silicon verification cycles.

Use Scenario: Timing source for SMPTE ST 2082 (12G-SDI) and ST 2083 (24G-SDI) video encoders/decoders in broadcast cameras and routers.

IC Role / Device Role / Timing Role: Low-drift VCXO providing 27 MHz, 74.25 MHz, 148.5 MHz, and 297 MHz clocks with ±20 ppm stability over wide ambient range.

Use Value: Prevents frame sync loss and lip-sync errors in multi-channel 4K/8K production workflows operating at –10 to +60 °C.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-frequency VCXO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si566ABA002531ACG	Same Si56x family, identical pinout and electrical specs, but fixed-frequency (single output) XO variant - no VC or FS pins.	Lacks frequency agility and voltage tuning; suitable only where clock tree requires static references.	Select only if system does not require dynamic frequency switching or PLL-based drift correction.
DS3202Z	Maxim Integrated dual-output VCXO; 200 fs jitter (12 kHz–20 MHz); 10–1000 MHz range; 5×7 mm package; no quad-frequency capability.	Supports only two frequencies; lower integration (no on-chip DSPLL, higher external component count).	Choose when dual-clock redundancy suffices and cost sensitivity outweighs jitter/performance advantages of Si567.

Compared with Si566ABA002531ACG and DS3202Z, the 567ABA002531ACG uniquely delivers four independently selectable, ultra-low-jitter outputs with integrated DSPLL and industry-leading PSNR - making it optimal for dense, multi-rate timing architectures where board space, jitter budget, and supply noise immunity are critical.

Availability

567ABA002531ACG is available at Aetrix Electronics and suitable for 100G/400G optical modules, high-end Ethernet switches, FPGA-based test equipment, and broadcast video infrastructure requiring stable component supply and rapid prototyping support.

Supply support for 567ABA002531ACG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global leader in semiconductor innovation, specializing in analog and mixed-signal technologies for wireless, broadband, automotive, and industrial markets.

The Si567 belongs to Skyworks' Ultra Series™ timing portfolio, engineered specifically for high-speed serial data applications demanding sub-150 fs jitter, multi-frequency flexibility, and robust operation in electrically noisy environments.

FAQ

What output formats does the 567ABA002531ACG support?

The 567ABA002531ACG is configured for LVPECL output per its ordering code 'A'. It does not support LVDS, CMOS, or HCSL in this specific variant. LVPECL provides differential signaling with 1.1–1.9 VPP swing and fast edge rates ideal for high-speed SerDes interfaces. Other output formats require different orderable SKUs (e.g., 'B' for LVDS).

How is frequency selection implemented on the 567ABA002531ACG?

The 567ABA002531ACG uses two dedicated pins - FS1 (pin 7) and FS0 (pin 8) - to select among four factory-programmed frequencies. Binary combinations (00, 01, 10, 11) activate each frequency in sequence. Both pins include internal 50 kΩ pull-ups to VDD, ensuring default selection on power-up unless actively driven.

What is the absolute pull range (APR) for the 567ABA002531ACG?

The 567ABA002531ACG has a Kv tuning slope of 60 ppm/V, yielding a minimum APR of ±20 ppm at 3.3 V. This includes worst-case contributions from temperature stability, initial accuracy, load pulling, VDD variation, and 20-year aging. APR defines the total frequency deviation the device can track over its lifetime under all operating conditions.

Does the 567ABA002531ACG require external configuration after soldering?

No. The 567ABA002531ACG is fully factory-programmed with its four frequencies, output format, OE polarity, and other parameters before shipment. No I²C, SPI, or OTP programming is needed in-system - it operates immediately upon power-up with valid FS pin states.

Can the 567ABA002531ACG operate from a 2.5 V supply?

Yes. Although ordered with 'A' (indicating 2.5/3.3 V VDD support), the 567ABA002531ACG operates across 2.5 V ±5% (2.375–2.625 V) and 3.3 V ±5% (3.135–3.465 V) without hardware changes. Internal regulation ensures consistent jitter and output swing performance across both rails.

567ABA002531ACG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Ultra™ Si567

Package/Case:: 8-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: VCXO

Frequency - Output 1:: 50.63282MHz, 142.8MHz, 216.666667MHz, 499.654MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: Enable/Disable

Output:: LVPECL

Voltage - Supply:: 2.5V ~ 3.3V

Frequency Stability:: ±20ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 170mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.052" (1.33mm)

Supplier Device Package:: -

567ABA002531ACG FAQ

1.How can I place an order for 567ABA002531ACG through Aetrix?

Please submit a Request for Quotation (RFQ) for 567ABA002531ACG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 567ABA002531ACG reliable?

The price and inventory of 567ABA002531ACG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 567ABA002531ACG is usually 5 days.

3.What payment methods are accepted for 567ABA002531ACG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 567ABA002531ACG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 567ABA002531ACG?

567ABA002531ACG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 567ABA002531ACG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 567ABA002531ACG?

For technical support, including 567ABA002531ACG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 567ABA002531ACG requirements.

6.How does Aetrix verify that 567ABA002531ACG is sourced from the original manufacturer or authorized distributors?

All 567ABA002531ACG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 567ABA002531ACG meets industry standards.

7.What is the process for return or replacement of 567ABA002531ACG?

All 567ABA002531ACG units undergo pre-shipment inspection (PSI). If there is an issue with 567ABA002531ACG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 567ABA002531ACG part is unused and in its original packaging.

Return procedure for 567ABA002531ACG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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