Analog Devices Inc. 5962-9559201MEA
- Part No.:
- 5962-9559201MEA
- Manufacturer:
- Analog Devices Inc.
- Category:
- Analog to Digital Converters (ADC)
- Package:
- -
- Datasheet:
-
5962-9559201MEA.pdf
- Description:
- IC ADC 16BIT SRL 100KSPS 16CDIP
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Product details
Overview
AD677JN from Analog Devices is a 16-bit, 100 kSPS autocalibrating successive-approximation ADC with on-chip sample-hold, serial output, ±5 V to ±10 V input range, and 1 MHz full-power bandwidth-used in precision instrumentation and data acquisition systems requiring high dc accuracy and dynamic performance.
For engineers reviewing the AD677JN datasheet, AD677JN pinout, AD677JN application, or AD677JN equivalent, key selection criteria include integral nonlinearity (±1 LSB typ), THD (–99 dB), S/(N+D) (92 dB), aperture jitter (100 ps), and dual-supply operation (+12 V/–12 V analog, +5 V digital).
Technical Context
The AD677JN implements a switched-capacitor charge-redistribution SAR architecture with on-chip microcoded controller and dual-die construction (BiMOS II analog + DSP CMOS digital chip). It performs 17-clock-cycle conversions with twos-complement serial output synchronized to SCLK.
Autocalibration corrects capacitor-matching errors via internal DAC and RAM-stored correction coefficients, enabling ±1 LSB INL without external trims. Input sampling is controlled by SAMPLE pin with 2 µs settling time, 6 ns aperture delay, and remote AGND SENSE for ground-referenced signal sources.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 16-bit-guarantees no missing codes across full scale |
| Conversion Rate | 100 kSPS-10 µs total conversion time enables real-time signal capture |
| INL | ±1 LSB (typ)-ensures linearity within 1 part in 65,536 for precision measurement |
| THD | –99 dB @ 100 kSPS-minimizes harmonic distortion in audio and IF sampling |
| S/(N+D) | 92 dB @ 100 kSPS-supports >15 ENOB in dynamic applications |
| Full-Power Bandwidth | 1 MHz-preserves amplitude fidelity for signals up to 1 MHz at full scale |
| Aperture Jitter | 100 ps rms-limits sampling uncertainty to <0.01% of 100 kSPS period |
Pinout & Package
AD677JN is housed in a 16-pin 0.3" narrow-body plastic DIP (N-16 package) with dual ground separation (AGND and DGND), dedicated analog reference (VREF), and isolated analog/digital supplies (VCC/VEE/VDD).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (SAMPLE) | Digital Input | Active-HIGH acquisition control; falling edge initiates conversion after 2 µs settling |
| 2 (CLK) | Digital Input | Master clock input; 17 pulses required per conversion; drives internal timing and SCLK generation |
| 3 (SDATA) | Digital Output | Serial twos-complement data output (MSB first); synchronized to SCLK rising edge |
| 4, 7 (DGND) | Power | Digital ground reference for VDD and logic outputs; must be isolated from AGND |
| 5 (VCC) | Power | +12 V analog supply for comparator, DAC, and input buffers; requires 0.1 µF local decoupling |
| 8 (AGND) | Power | Analog ground return for VIN, VREF, and internal analog circuitry; connects to system analog common |
| 9 (AGND SENSE) | Analog Input | Remote sensing point for analog ground potential-reduces error from ground loop voltage drops |
| 10 (VIN) | Analog Input | Differential input with ±VREF range; 50 pF input capacitance during sample phase |
| 11 (VREF) | Analog Input | External reference input (5 V to 10 V); sets full-scale range and directly impacts INL and gain error |
| 12 (VEE) | Power | –12 V analog supply; powers negative rail circuits including comparator and charge redistribution array |
| 13, 14 (VDD) | Power | +5 V digital supply for controller, RAM, and output drivers; separate from analog supplies to limit crosstalk |
| 15 (SCLK) | Digital Output | Derived clock for SDATA readout; phase-aligned to CLK with defined setup/hold margins |
| 16 (BUSY) | Digital Output | Active-HIGH status flag indicating conversion or calibration in progress; used for handshaking |
| 16 (CAL) | Digital Input | Asynchronous calibration trigger; HIGH resets internal state, LOW starts 85,532-clock autocal sequence |
Key Features
| Feature | Design Value |
|---|---|
| On-chip autocalibration | Eliminates need for external trim pots or user calibration-stores correction coefficients in on-chip RAM |
| Integrated sample-hold | Removes requirement for external SHA; supports 2 µs input settling and 100 ps aperture jitter |
| Separate analog/digital grounds | Reduces digital switching noise coupling into analog path-critical for >90 dB SFDR performance |
| TTL-compatible I/O | Allows direct interface to standard logic families without level-shifting-VIH = 2.0 V, VOL = 0.4 V |
| Remote AGND sense | Compensates for ground potential differences between signal source and ADC-improves offset stability |
Applications
| High-Accuracy Data Loggers | Industrial Process Monitoring |
|---|---|
Use Scenario: Continuous logging of temperature, pressure, and strain sensor outputs over 0°C to +70°C with <0.01% full-scale error. IC Role / Device Role / Timing Role: Primary 16-bit ADC capturing bipolar analog inputs at 10–100 kSPS with post-calibration INL ≤ ±1 LSB. Use Value: Autocalibration maintains dc accuracy without field recalibration; AGND SENSE rejects ground-loop-induced offset drift. | Use Scenario: Real-time monitoring of motor current, voltage, and vibration in PLC-controlled factory equipment. IC Role / Device Role / Timing Role: High-fidelity digitization of conditioned analog signals prior to FPGA-based analysis or HMI display. Use Value: 92 dB S/(N+D) and –99 dB THD ensure clean spectral representation for FFT-based fault detection algorithms. |
| Test & Measurement Equipment | Medical Signal Acquisition |
Use Scenario: Digitizing low-level sensor outputs in benchtop multimeters and automated test systems requiring traceable metrology. IC Role / Device Role / Timing Role: Precision front-end ADC with calibrated gain/offset tracking across temperature and supply variations. Use Value: ±0.5 LSB temperature drift and ±0.5 LSB power supply rejection enable stable readings without periodic zeroing. | Use Scenario: Capturing ECG, EEG, and EMG waveforms in portable diagnostic devices where size and power are constrained. IC Role / Device Role / Timing Role: Low-noise, low-jitter ADC interfacing to instrumentation amplifiers with ±5 V output swing. Use Value: 160 µV rms input noise and 1 MHz bandwidth support high-fidelity biopotential waveform capture without aliasing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit SAR ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AD7606-6 | 8-channel simultaneous-sampling, integrated PGA and reference; 200 kSPS per channel; no autocalibration | Multi-channel data acquisition vs. single-channel high-accuracy measurement | Select AD7606-6 when synchronizing multiple sensors is required; AD677JN preferred for lowest INL in single-channel systems |
| ADS8860 | 16-bit, 1 MSPS, SPI interface, internal reference; no external VREF option; ±2.5 V input range only | High-speed portable instrumentation vs. lab-grade dc-critical systems | Select ADS8860 for compact battery-powered designs; AD677JN retains flexibility with ±5/±10 V ranges and superior dc specs |
Compared with AD7606-6 and ADS8860, the AD677JN delivers best-in-class dc accuracy (±1 LSB INL) and lowest aperture jitter (100 ps), making it optimal for metrology-grade single-channel applications where long-term stability and minimal user calibration are mandatory.
Availability
AD677JN is available at Aetrix Electronics and suitable for high-accuracy data loggers, industrial process monitoring, test & measurement equipment, and medical signal acquisition requiring stable component supply and long-lifecycle support.
Supply support for AD677JN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The AD677JN belongs to Analog Devices' precision SAR ADC product line, engineered for applications demanding uncompromised dc accuracy, low noise, and robust dynamic performance in instrumentation and industrial control systems.
FAQ
What is the maximum recommended clock frequency for reliable operation of the AD677JN?
The AD677JN requires a minimum CLK period of 480 ns (2.08 MHz max), but 580 ns (1.72 MHz) is recommended for optimal accuracy over temperature. Exceeding this limit risks violating tCLK timing margins, degrading INL and THD. The device uses 17 CLK pulses per conversion, so 100 kSPS operation requires ≥1.7 MHz clock-verified in datasheet Figure 2 and Timing Specifications table.
Does the AD677JN require external calibration components or user trimming?
No, the AD677JN does not require external calibration components or user trimming. Its on-chip autocalibration circuit measures and stores capacitor-matching error corrections in internal RAM during each CAL cycle. Post-calibration, AD677JN achieves ±1 LSB INL without any external adjustments-confirmed in Product Highlights and Functional Description sections.
Can the AD677JN operate with a 5 V reference voltage, and how does that affect its specifications?
Yes, the AD677JN supports VREF from 5 V to 10 V. At 5 V reference, full-scale input range is ±5 V, power consumption drops to 360 mW (vs. 450 mW at 10 V), and dynamic performance remains specified (e.g., 92 dB S/(N+D) maintained). DC specs like INL and offset error are unchanged-per DC Specifications table footnote 4 and Applications section recommendations.
What is the purpose of the AGND SENSE pin on the AD677JN, and how should it be connected?
The AGND SENSE pin on the AD677JN provides remote sensing of the analog ground potential at the signal source to compensate for voltage drops in ground traces. It must be connected directly to the local ground reference point of the input signal source-not to the ADC's AGND pad-to eliminate ground-loop-induced offset errors, as detailed in the Analog Input section and Figure 4 grounding diagram.
How does the AD677JN handle out-of-range input voltages, and what output coding is used?
The AD677JN limits output coding for out-of-range inputs using twos-complement format: inputs exceeding +FS output 011...11; inputs below –FS output 100...00. This clamping behavior prevents erroneous code transitions and ensures deterministic saturation-explicitly defined in Table I and General Conversion Guidelines section of the datasheet.
5962-9559201MEA Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tube
- Product Status:
- Active
- Number of Bits:
- -
- Sampling Rate (Per Second):
- -
- Number of Inputs:
- -
- Input Type:
- -
- Data Interface:
- -
- Configuration:
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- Ratio - S/H:ADC:
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- Number of A/D Converters:
- -
- Architecture:
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- Reference Type:
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- Voltage - Supply, Analog:
- -
- Voltage - Supply, Digital:
- -
- Features:
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- Operating Temperature:
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- Supplier Device Package:
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