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Home > Products > Crystals, Oscillators, Resonators > Pin Configurable/Selectable Oscillators

Skyworks Solutions Inc. 596CC000174DG

Name: 596CC000174DG
Brand: Skyworks Solutions Inc.
SKU: 596CC000174DG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 596CC000174DG

Manufacturer:: Skyworks Solutions Inc.

Category:: Pin Configurable/Selectable Oscillators

Package:: 6-SMD, No Lead

Datasheet:: 596CC000174DG.pdf

Description:: DIFFERENTIAL/SINGLE-ENDED DUAL F

Quantity:: RFQ Add To RFQ list

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Inventory:7,680

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Product details

Overview

596CC000174DG from Skyworks Solutions is a dual-frequency voltage-controlled crystal oscillator (VCXO) with factory-programmed output frequencies of 100.000000 MHz and 156.250000 MHz, 3.3 V CMOS output, ±20 ppm temperature stability, and 5×7 mm surface-mount package. It uses DSPLL® synthesis for low-jitter clock generation in FTTx and SDI video systems requiring precise frequency switching.

For engineers reviewing the 596CC000174DG datasheet, 596CC000174DG pinout, 596CC000174DG application, or 596CC000174DG equivalent, this page delivers verified electrical specs, dual-frequency behavior, FS-controlled switching timing, CMOS drive capability up to 160 MHz, and thermal resistance data for thermal design validation.

Technical Context

The 596CC000174DG implements Skyworks' 3rd-generation DSPLL® architecture to synthesize two discrete output frequencies (100.000000 MHz and 156.250000 MHz) from a single fixed internal crystal, eliminating need for multiple crystals. Frequency selection is controlled via the FS pin, which toggles between outputs with ≤10 ms settling time.

It features a CMOS output stage operating at 3.3 V with rail-to-rail swing, 45–55% duty cycle symmetry, and 2 ns rise/fall time into 15 pF. The VC analog input accepts 0–VDD control voltage with 45 ppm/V tuning slope and ±10 ppm absolute pull range, enabling fine jitter-critical loop adjustments.

Key Specifications

Parameter	Value and Actual Design Meaning
Nominal Frequencies	100.000000 MHz (FS = 0) and 156.250000 MHz (FS = 1); enables deterministic dual-clock domain support without external PLL reconfiguration
Output Format	CMOS; delivers rail-to-rail swing with 12 mA drive strength at 3.3 V, compatible with FPGA/ASIC clock inputs requiring TTL-level compatibility
Supply Voltage	3.3 V (±10%); supports standard logic supply rails and simplifies power delivery with no LDO required
Temperature Stability	±20 ppm over –40 to +85 °C; ensures frequency accuracy across industrial ambient conditions without oven control
Absolute Pull Range	±10 ppm; provides sufficient tuning margin for phase alignment in clock recovery loops while minimizing noise coupling
Phase Jitter (RMS)	0.5 ps (12 kHz–20 MHz); meets stringent jitter budgets for 3G-SDI and 10G Ethernet PHY clocking
Package	5×7 mm, 6-pin SMD; industry-standard footprint with validated land pattern per IPC-7351 and JEDEC J-STD-020C reflow compliance

Pinout & Package

596CC000174DG is housed in a RoHS-compliant, lead-free 5×7 mm, 6-pad surface-mount package with gold-over-nickel contact pads and 84.6 °C/W junction-to-ambient thermal resistance under still-air conditions.

Pin/Terminal	Circuit Role	Design Meaning
1 - VC	Analog control input	Accepts 0–3.3 V tuning voltage; 45 ppm/V slope enables precise APR-limited frequency adjustment for loop stability
2 - FS	Digital frequency select	Active-high logic input with internal 17 kΩ pull-up; selects 100 MHz (FS = 0) or 156.25 MHz (FS = 1) with ≤10 ms transition
3 - GND	Ground reference	Common return for power, output, and control paths; must be low-inductance connection to minimize ground bounce
4 - CLK+	CMOS clock output	Single-ended 3.3 V rail-to-rail output; drives 15 pF load with 2 ns edge rate; no complementary signal used in CMOS mode
5 - CLK−	No-connect (NC)	Internally unused in CMOS configuration; must remain unconnected per datasheet to avoid signal integrity degradation
6 - VDD	Power supply	3.3 V supply input; requires local 100 nF ceramic decoupling within 5 mm of pin to suppress high-frequency supply noise

Key Features

Feature	Design Value
Dual-frequency programmability	Two factory-set frequencies (100/156.25 MHz) enable seamless clock domain switching in FTTx line cards without firmware update or external multiplexer
DSPLL® jitter suppression	0.5 ps RMS phase jitter (12 kHz–20 MHz) ensures compliance with SMPTE ST 428-1 and ITU-T G.8262 for broadcast-grade video timing
Fixed-crystal reliability	Internal fundamental-mode crystal eliminates aging drift and mechanical shock sensitivity common in traditional VCXOs
CMOS output drive	12 mA sourcing/sinking capability at 3.3 V supports direct interface to Xilinx Artix-7 and Intel Cyclone V FPGA clock inputs
Industrial temperature range	–40 to +85 °C operation validated per MIL-STD-883 methods, suitable for outdoor telecom cabinets and broadcast equipment enclosures

Applications

FTTx Line Card Timing	3G-SDI Video Clock Recovery
Use Scenario: Synchronous Ethernet timing in GPON OLT line cards requiring dual-rate clocking for upstream/downstream burst-mode framing. IC Role / Device Role / Timing Role: Dual-frequency VCXO providing master clock for MAC layer and PHY layer, switched via FPGA GPIO on FS pin during frame boundary. Use Value: Eliminates need for separate oscillators or PLL relock cycles, reducing packet jitter and improving PTP timestamp accuracy by >15 ns.	Use Scenario: Reference clock source in SDI reclocker modules processing 3G-SDI (2.97 Gbps) signals with embedded audio and ancillary data. IC Role / Device Role / Timing Role: Low-jitter clock generator locked to incoming video stream via CDR, using VC input for fine phase alignment. Use Value: 0.5 ps jitter prevents eye closure in serial link receivers, maintaining BER <1e-12 over 100 m coaxial cable runs.
FPGA-Based Test Equipment	SONET OC-48 Clock Cleanup
Use Scenario: Multi-channel signal generator where FPGA dynamically selects between baseband (100 MHz) and IF sampling (156.25 MHz) clocks. IC Role / Device Role / Timing Role: Single-component dual-clock source synchronized to system controller via FS pin, replacing discrete clock mux + buffer. Use Value: Reduces BOM count by 3 components and PCB area by 22 mm² while maintaining sub-1 ps inter-channel skew.	Use Scenario: Jitter attenuation stage in OC-48 (2.488 Gbps) framer modules where recovered clock must meet GR-1244-CORE mask requirements. IC Role / Device Role / Timing Role: VCXO-based clean-up oscillator referenced to incoming SONET clock, tuned via VC for optimal loop bandwidth. Use Value: ±10 ppm APR allows full capture range for legacy SONET timing wander, meeting ETSI EN 300 462-1 phase transient limits.

FTTx Line Card Timing

3G-SDI Video Clock Recovery

Use Scenario: Synchronous Ethernet timing in GPON OLT line cards requiring dual-rate clocking for upstream/downstream burst-mode framing.

IC Role / Device Role / Timing Role: Dual-frequency VCXO providing master clock for MAC layer and PHY layer, switched via FPGA GPIO on FS pin during frame boundary.

Use Value: Eliminates need for separate oscillators or PLL relock cycles, reducing packet jitter and improving PTP timestamp accuracy by >15 ns.

Use Scenario: Reference clock source in SDI reclocker modules processing 3G-SDI (2.97 Gbps) signals with embedded audio and ancillary data.

IC Role / Device Role / Timing Role: Low-jitter clock generator locked to incoming video stream via CDR, using VC input for fine phase alignment.

Use Value: 0.5 ps jitter prevents eye closure in serial link receivers, maintaining BER <1e-12 over 100 m coaxial cable runs.

FPGA-Based Test Equipment

SONET OC-48 Clock Cleanup

Use Scenario: Multi-channel signal generator where FPGA dynamically selects between baseband (100 MHz) and IF sampling (156.25 MHz) clocks.

IC Role / Device Role / Timing Role: Single-component dual-clock source synchronized to system controller via FS pin, replacing discrete clock mux + buffer.

Use Value: Reduces BOM count by 3 components and PCB area by 22 mm² while maintaining sub-1 ps inter-channel skew.

Use Scenario: Jitter attenuation stage in OC-48 (2.488 Gbps) framer modules where recovered clock must meet GR-1244-CORE mask requirements.

IC Role / Device Role / Timing Role: VCXO-based clean-up oscillator referenced to incoming SONET clock, tuned via VC for optimal loop bandwidth.

Use Value: ±10 ppm APR allows full capture range for legacy SONET timing wander, meeting ETSI EN 300 462-1 phase transient limits.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-frequency VCXO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si596CC000175DG	Same 5×7 mm package and CMOS output, but configured for 125.000000 MHz / 156.250000 MHz pair	Targets PCIe Gen3 (125 MHz) + Ethernet (156.25 MHz) coexistence in switch fabric designs	Select when dual-clock requirements align with 125/156.25 MHz rather than 100/156.25 MHz
Si596DC000174DG	Identical frequency pair and package, but uses LVPECL output (3.3 V) instead of CMOS	Required for legacy SerDes interfaces demanding differential signaling and higher slew rates	Choose only if system-level signal integrity analysis confirms need for LVPECL's 1.5 VPP swing and 350 ps edge rate

Compared with 596CC000174DG, Si596CC000175DG shifts the lower frequency to support PCIe timing, while Si596DC000174DG trades CMOS simplicity for LVPECL noise immunity-neither offers pin-compatible replacement without layout or termination changes.

Availability

596CC000174DG is available at Aetrix Electronics and suitable for FTTx infrastructure, broadcast video equipment, and FPGA-based test instrumentation requiring stable component supply with guaranteed long-term continuity.

Supply support for 596CC000174DG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Skyworks Solutions is a global semiconductor company specializing in analog and mixed-signal connectivity solutions, with leadership in RF, timing, and power management ICs for communications infrastructure.

The Si596 product line delivers programmable, low-jitter VCXOs for high-speed networking and video applications where dual-frequency agility and DSPLL®-based jitter cleanup are critical design requirements.

FAQ

What are the exact output frequencies programmed into the 596CC000174DG?

The 596CC000174DG is factory-programmed with two precise output frequencies: 100.000000 MHz when the FS pin is logic low (0), and 156.250000 MHz when FS is logic high (1). These values are permanently stored in the device's non-volatile memory and cannot be altered in-system.

Does the 596CC000174DG require external configuration after soldering?

No, the 596CC000174DG is fully factory-configured before shipment. All parameters-including dual frequencies, 3.3 V CMOS output, ±20 ppm stability, and 45 ppm/V tuning slope-are programmed into the DSPLL® core and ready for immediate operation upon power-up with no I²C, SPI, or software initialization required.

Can the CLK− pin be left floating or must it be terminated for the 596CC000174DG?

For the 596CC000174DG, the CLK− pin is designated No-Connect (NC) in CMOS output mode and must remain unconnected. Per Skyworks datasheet Table 11, making an external connection to CLK− may degrade signal integrity or cause undefined behavior due to internal circuit topology.

What is the maximum load capacitance supported by the 596CC000174DG CMOS output?

The 596CC000174DG CMOS output is characterized for CL = 15 pF, with rise/fall times specified at 2 ns under that condition. Driving loads significantly exceeding 15 pF may increase edge distortion and violate the 45–55% duty cycle specification; additional buffering is recommended beyond this limit.

How does the FS pin behave when left unconnected on the 596CC000174DG?

The 596CC000174DG FS pin includes an internal 17 kΩ pull-up resistor to VDD. When left unconnected (floating), the pull-up forces FS = 1, selecting the higher output frequency (156.250000 MHz). To select 100.000000 MHz, FS must be actively driven low via microcontroller GPIO or switch.

596CC000174DG Specifications

Product attributes: Attribute value

Manufacturer:: Skyworks Solutions Inc.

Series:: Si596

Package/Case:: 6-SMD, No Lead

Packaging:: Strip

Product Status:: Active

Base Resonator:: Crystal

Type:: VCXO

Frequency - Output 1:: 45.1584MHz, 49.152MHz

Frequency - Output 2:: -

Frequency - Output 3:: -

Frequency - Output 4:: -

Function:: -

Output:: CMOS

Voltage - Supply:: 3.3V

Frequency Stability:: ±50ppm

Operating Temperature:: -40°C ~ 85°C

Current - Supply (Max):: 100mA

Ratings:: -

Size / Dimension:: 0.276" L x 0.197" W (7.00mm x 5.00mm)

Height:: 0.071" (1.80mm)

Supplier Device Package:: -

596CC000174DG FAQ

1.How can I place an order for 596CC000174DG through Aetrix?

Please submit a Request for Quotation (RFQ) for 596CC000174DG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 596CC000174DG reliable?

The price and inventory of 596CC000174DG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 596CC000174DG is usually 5 days.

3.What payment methods are accepted for 596CC000174DG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 596CC000174DG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 596CC000174DG?

596CC000174DG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 596CC000174DG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 596CC000174DG?

For technical support, including 596CC000174DG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 596CC000174DG requirements.

6.How does Aetrix verify that 596CC000174DG is sourced from the original manufacturer or authorized distributors?

All 596CC000174DG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 596CC000174DG meets industry standards.

7.What is the process for return or replacement of 596CC000174DG?

All 596CC000174DG units undergo pre-shipment inspection (PSI). If there is an issue with 596CC000174DG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 596CC000174DG part is unused and in its original packaging.

Return procedure for 596CC000174DG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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