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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Renesas 5P35021-129NDGI

Name: 5P35021-129NDGI
Brand: Renesas
SKU: 5P35021-129NDGI
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 5P35021-129NDGI

Manufacturer:: Renesas

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: -

Datasheet:: 5P35021-129NDGI.pdf

Description:: IC CLOCK GENERATOR 20QFN

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Product details

Overview

5P35021-129NDGI from Renesas Electronics is a VersaClock® programmable clock generator with three independent PLLs, supporting up to six frequency outputs including PCIe Gen3-compliant clocks (phase jitter ≤ 1.5 ps RMS, 12 kHz–20 MHz), LVCMOS/LVDS/LVPECL/LP-HCSL differential and single-ended outputs, and ultra-low-power 32.768 kHz RTC output (< 2 µA). It serves as a high-performance, low-power timing solution for PCIe Gen1–3 systems and consumer computing platforms.

For engineers reviewing the 5P35021-129NDGI datasheet, 5P35021-129NDGI pinout, 5P35021-129NDGI application, or 5P35021-129NDGI equivalent, this device offers I2C-configurable register settings, OTP-stored configuration, Proactive Power Saving (PPS), Dynamic Frequency Control (DFC), and spread-spectrum support - critical for EMI reduction, power-aware system sleep modes, and multi-frequency SoC clocking.

Technical Context

The 5P35021-129NDGI implements a triple-PLL architecture: PLL1 supports analog spread spectrum and drives DIFF1/SE1; PLL2 supports digital spread spectrum and DFC with four VCO frequencies; PLL3 provides integer-N synthesis for SE1 and reference division. Each PLL features independently programmable bandwidth, divider ratios, and source selection (crystal, differential input, or internal DCO).

Its output routing includes five configurable clock outputs: one dedicated LVCMOS (SE1, 1–160 MHz), two differential pairs (DIFF1/DIFF1B and DIFF2/DIFF2B, 1–500 MHz, supporting LVCMOS/LP-HCSL/LVDS/LVPECL), and a battery-backed 32.768 kHz DCO on SE1. Power management integrates PPS (auto-switch to 32 kHz on system sleep), PPB (performance-power balancing), and ORT (VCO overshoot suppression during DFC transitions).

Key Specifications

Parameter	Value and Actual Design Meaning
PCIe Gen3 phase jitter	≤1.5 ps RMS (12 kHz–20 MHz); meets PCIe Gen3 clock compliance for root complex and endpoint timing budgets.
Output count & types	Up to 6 outputs: 1× LVCMOS SE1 (1–160 MHz), 2× differential pairs (DIFF1/DIFF1B, DIFF2/DIFF2B; 1–500 MHz), plus 32.768 kHz DCO.
PLL architecture	Three independent PLLs: PLL1 (analog SS), PLL2 (digital SS + DFC), PLL3 (integer-N); each with programmable M/N dividers and source mux.
Configuration storage	On-chip OTP memory stores one full configuration; enables autonomous boot-up without external programming.
Power supply options	VDD33 (3.3 V), VDDA (3.3 V), VDDSE1 (1.8–3.3 V), VDDDIFF1/2 (2.5–3.3 V), VBAT (2.5–3.3 V for 32 kHz DCO).
Operating temperature	Automotive Grade 2: –40°C to +105°C; qualified per AEC-Q100; suitable for infotainment and ADAS timing.
I²C interface	Standard-mode (100 kHz) and fast-mode (400 kHz); used for runtime register updates, DFC control, and OTP programming.

Pinout & Package

5P35021-129NDGI is housed in a 3 mm × 3 mm, 20-pin Very Thin Quad Flat No-Lead (VFQFPN) package with exposed thermal pad (EPAD). Pin assignments follow JEDEC MO-220WEED, with dedicated power domains per output bank (VDDSE1, VDDDIFF1, VDDDIFF2) and isolated ground returns (VSSSE1, VSSDIFF1, VSSDIFF2).

Pin/Terminal	Circuit Role	Design Meaning
1, 8, VDDA, VDD33	Analog & core power supply	3.3 V supplies for PLLs, I²C engine, and logic; must be decoupled locally.
2, 3, SDA_DFC0, SEL_DFC/SCL_DFC1	I²C data / DFC control or I²C clock / DFC latch	Configurable dual-function pins: I²C mode (default) or hardware DFC control via power-on latch on SEL_DFC.
4, 5, CLKIN/X2, CLKINB/X1	Clock reference input	Supports crystal (8–40 MHz) or differential LVDS/LVPECL (8–125 MHz); X1/X2 internally biased for crystal mode.
6, VBAT	RTC backup supply	Connects to coin cell (2.5–3.3 V); powers only 32.768 kHz DCO when main VDD drops below 2.3 V.
10, 13, 17, VDDSE1, VDDDIFF1, VDDDIFF2	Output-specific power rails	Independent voltage setting per output bank: sets LVCMOS logic level (VDDSE1), differential swing (VDDDIFF1/2).
11, SE1	Primary single-ended output	Programmable source (REF, PLL2, PLL3, or 32.768 kHz DCO); supports 1–160 MHz LVCMOS.
12, OE1	Multi-function control pin	OTP-configurable as OE, PD#, PPS input, DFC0, or RESET out - enables system-level power coordination.
14–15, 18–19, DIFF1B/DIFF1, DIFF2B/DIFF2	Differential clock outputs	Each pair supports LVCMOS/LP-HCSL/LVDS/LVPECL; output type and termination set via OTP/I²C registers.

Key Features

Feature	Design Value
Proactive Power Saving (PPS)	Auto-detects host power-down state and switches SE1 to 32.768 kHz DCO (<2 µA), preserving RTC accuracy without software intervention.
Dynamic Frequency Control (DFC)	Hardware- or I²C-triggered smooth transition between four pre-programmed PLL2 VCO frequencies - no glitch or overshoot due to ORT.
Overshoot Reduction Technology (ORT)	Actively regulates VCO tuning current during frequency changes, eliminating clock spikes and ensuring <10 ns transient duration.
Spread spectrum generation	PLL1 (analog SS) and PLL2 (digital SS) independently reduce EMI; configurable down-spread or center-spread at 32 kHz modulation rate.
Crystal tuning capacitors	Two 8-bit programmable internal caps (0–15 pF in 1 pF steps) per crystal terminal - eliminates external load caps and simplifies BOM.

Applications

PCIe Gen3 Root Complex Timing	Automotive Infotainment SoC Clocking
Use Scenario: Provides reference clocks to CPU, GPU, and PCIe switch in notebook/desktop motherboards requiring Gen3 compliance. IC Role / Device Role / Timing Role: Primary clock generator delivering synchronized 100 MHz PCIe REFCLK, 125 MHz SATA, and 25 MHz USB clocks. Use Value: Meets PCIe Gen3 phase jitter spec (≤1.5 ps RMS) while enabling dynamic frequency scaling via DFC to reduce idle power.	Use Scenario: Supplies multiple domain clocks to Tegra or i.MX8-based head units with display, audio, and camera subsystems. IC Role / Device Role / Timing Role: Single-chip timing source for display pixel clock (148.5 MHz LVDS), audio master clock (12.288 MHz), and CAN FD controller clock (40 MHz). Use Value: AEC-Q100 Grade 2 qualification and –40°C to +105°C operation ensure reliability; PPS extends battery life during vehicle key-off.
Smartphone/Tablet Baseband Timing	Industrial Edge Gateway Synchronization
Use Scenario: Replaces multiple discrete crystals in compact mobile platforms where board space and power are constrained. IC Role / Device Role / Timing Role: Generates 38.4 MHz RF synthesizer clock, 19.2 MHz UART clock, and 32.768 kHz RTC clock from one device. Use Value: Ultra-low 32.768 kHz DCO current (<2 µA) enables multi-year RTC operation on button cell; LVCMOS outputs drive baseband ASIC directly.	Use Scenario: Delivers precise time-aligned clocks to FPGA, Ethernet PHY, and real-time MCU in IIoT gateways requiring IEEE 1588 PTP support. IC Role / Device Role / Timing Role: Provides 125 MHz SGMII clock, 10 MHz PTP reference, and 1 PPS sync pulse derived from GPS-disciplined oscillator input. Use Value: Three independent PLLs allow separate jitter-optimized paths: low-jitter for Ethernet, stable integer-N for PTP, and SS-enabled for EMI-sensitive RF sections.

PCIe Gen3 Root Complex Timing

Automotive Infotainment SoC Clocking

Use Scenario: Provides reference clocks to CPU, GPU, and PCIe switch in notebook/desktop motherboards requiring Gen3 compliance.

IC Role / Device Role / Timing Role: Primary clock generator delivering synchronized 100 MHz PCIe REFCLK, 125 MHz SATA, and 25 MHz USB clocks.

Use Value: Meets PCIe Gen3 phase jitter spec (≤1.5 ps RMS) while enabling dynamic frequency scaling via DFC to reduce idle power.

Use Scenario: Supplies multiple domain clocks to Tegra or i.MX8-based head units with display, audio, and camera subsystems.

IC Role / Device Role / Timing Role: Single-chip timing source for display pixel clock (148.5 MHz LVDS), audio master clock (12.288 MHz), and CAN FD controller clock (40 MHz).

Use Value: AEC-Q100 Grade 2 qualification and –40°C to +105°C operation ensure reliability; PPS extends battery life during vehicle key-off.

Smartphone/Tablet Baseband Timing

Industrial Edge Gateway Synchronization

Use Scenario: Replaces multiple discrete crystals in compact mobile platforms where board space and power are constrained.

IC Role / Device Role / Timing Role: Generates 38.4 MHz RF synthesizer clock, 19.2 MHz UART clock, and 32.768 kHz RTC clock from one device.

Use Value: Ultra-low 32.768 kHz DCO current (<2 µA) enables multi-year RTC operation on button cell; LVCMOS outputs drive baseband ASIC directly.

Use Scenario: Delivers precise time-aligned clocks to FPGA, Ethernet PHY, and real-time MCU in IIoT gateways requiring IEEE 1588 PTP support.

IC Role / Device Role / Timing Role: Provides 125 MHz SGMII clock, 10 MHz PTP reference, and 1 PPS sync pulse derived from GPS-disciplined oscillator input.

Use Value: Three independent PLLs allow separate jitter-optimized paths: low-jitter for Ethernet, stable integer-N for PTP, and SS-enabled for EMI-sensitive RF sections.

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable clock generator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
IDT 5P49V5901B000NLGI	Single PLL, 4-output, no DFC or PPS; supports only LVDS/LVPECL; no VBAT or 32.768 kHz DCO.	Lacks automotive temp grade and RTC backup; suited for cost-sensitive non-automotive PCIe add-in cards.	Select when only basic PCIe Gen2 timing is needed and DFC/PPS/RTC are unnecessary.
Renesas 5P49V60-001NDGI	Four PLLs, 8 outputs, integrated EEPROM, higher max frequency (750 MHz), but no ORT or VBAT support.	Targets high-end servers and AI accelerators; lacks battery-backed RTC and automotive qualification.	Choose for multi-processor SoC clock trees needing >500 MHz outputs and EEPROM persistence, not automotive or ultra-low-power RTC.

Compared with 5P49V5901B000NLGI and 5P49V60-001NDGI, the 5P35021-129NDGI uniquely balances automotive-grade reliability, ultra-low-power RTC capability, and on-the-fly frequency agility - making it optimal for power-constrained, safety-aware embedded systems rather than pure performance or cost-driven designs.

Availability

5P35021-129NDGI is available at Aetrix Electronics and suitable for PCIe Gen3 timing, automotive infotainment, and industrial edge gateway applications requiring stable component supply, AEC-Q100 qualification, and long-term lifecycle support.

Supply support for 5P35021-129NDGI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and timing solutions for automotive, industrial, and enterprise markets.

The 5P35021-129NDGI belongs to Renesas' VersaClock® family of programmable clock generators, designed specifically for low-power, high-flexibility timing in PCIe, consumer, and automotive applications - emphasizing configurability, EMI reduction, and system-level power awareness.

FAQ

What is the primary clock output capability of the 5P35021-129NDGI?

The 5P35021-129NDGI delivers up to six programmable clock outputs: one LVCMOS single-ended output (SE1, 1–160 MHz), two differential pairs (DIFF1/DIFF1B and DIFF2/DIFF2B, 1–500 MHz), and a dedicated 32.768 kHz DCO output. All outputs are independently configurable for format (LVCMOS/LVDS/LVPECL/LP-HCSL), frequency, and source (crystal, PLL1/2/3, or DCO). The 5P35021-129NDGI supports PCIe Gen3-compliant jitter performance on its primary outputs.

How does the Proactive Power Saving (PPS) function operate in the 5P35021-129NDGI?

The 5P35021-129NDGI's PPS function uses the OE1 pin as an input to detect host system power-down states. When asserted, it automatically switches the SE1 output from its active-frequency clock to the ultra-low-power 32.768 kHz DCO (<2 µA), preserving RTC functionality without firmware involvement. This behavior is hardware-automated and requires no I²C command - the 5P35021-129NDGI maintains timing continuity during sleep modes.

Can the 5P35021-129NDGI generate spread spectrum clocks, and which PLLs support it?

Yes, the 5P35021-129NDGI supports spread spectrum clocking on two PLLs: PLL1 implements analog spread spectrum, and PLL2 implements digital spread spectrum. Both support configurable down-spread or center-spread modes at a 32 kHz modulation rate. Spread spectrum is enabled per-PLL via OTP or I²C registers and is used to reduce electromagnetic interference (EMI) in noise-sensitive systems - a key feature of the 5P35021-129NDGI for automotive and computing applications.

What package and pin count does the 5P35021-129NDGI use, and what are its thermal characteristics?

The 5P35021-129NDGI uses a 3 mm × 3 mm, 20-pin Very Thin Quad Flat No-Lead (VFQFPN) package with exposed thermal pad (EPAD). Its thermal resistance θ_JA is 120°C/W (JEDEC JESD51-7, 2-layer board), and it supports junction temperatures from –40°C to +125°C. The package enables high-density PCB layouts and efficient heat dissipation - critical for automotive and industrial deployments where ambient temperatures reach +105°C, as certified under AEC-Q100 Grade 2 for the 5P35021-129NDGI.

Is the 5P35021-129NDGI compatible with crystal inputs, and what tuning range does it support?

Yes, the 5P35021-129NDGI accepts fundamental-mode quartz crystals from 8 MHz to 40 MHz on its X1/X2 pins. It includes two independent 8-bit programmable tuning capacitors (0–15 pF in 1 pF steps) - one at each crystal terminal - to match vendor-specified load capacitance and eliminate external capacitors. This calibration ensures ±10 ppm frequency accuracy across temperature and aging, a core capability confirmed in the 5P35021-129NDGI datasheet and essential for stable system timing.

5P35021-129NDGI Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: *

Package/Case:: -

Packaging:: Bulk

Product Status:: Obsolete

Programmable:: Not Verified

Type:: -

PLL:: -

Input:: -

Output:: -

Number of Circuits:: -

Ratio - Input:Output:: -

Differential - Input:Output:: -

Frequency - Max:: -

Divider/Multiplier:: -

Voltage - Supply:: -

Operating Temperature:: -

Mounting Type:: -

Grade:: -

Qualification:: -

Supplier Device Package:: -

5P35021-129NDGI FAQ

1.How can I place an order for 5P35021-129NDGI through Aetrix?

Please submit a Request for Quotation (RFQ) for 5P35021-129NDGI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 5P35021-129NDGI reliable?

The price and inventory of 5P35021-129NDGI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 5P35021-129NDGI is usually 5 days.

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5P35021-129NDGI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 5P35021-129NDGI order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 5P35021-129NDGI?

For technical support, including 5P35021-129NDGI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 5P35021-129NDGI requirements.

6.How does Aetrix verify that 5P35021-129NDGI is sourced from the original manufacturer or authorized distributors?

All 5P35021-129NDGI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 5P35021-129NDGI meets industry standards.

7.What is the process for return or replacement of 5P35021-129NDGI?

All 5P35021-129NDGI units undergo pre-shipment inspection (PSI). If there is an issue with 5P35021-129NDGI, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 5P35021-129NDGI part is unused and in its original packaging.

Return procedure for 5P35021-129NDGI:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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