Renesas 6116LA35TDB
- Part No.:
- 6116LA35TDB
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 24-CDIP (0.300", 7.62mm)
- Datasheet:
-
6116LA35TDB.pdf
- Description:
- IC SRAM 16KBIT PARALLEL 24CDIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,788
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Product details
Overview
6116LA35TDB from Renesas Electronics is a 16K-bit (2K × 8) low-power CMOS static RAM with 35ns access time, TTL-compatible I/O, and battery backup data retention at 2V. It operates across –55°C to +125°C (military grade), features automatic standby mode on chip select high, and is housed in a 24-pin ceramic DIP (SD24) package. Used in avionics control modules requiring non-refreshed memory with extended data hold under brownout.
For engineers reviewing the 6116LA35TDB datasheet, 6116LA35TDB pinout, 6116LA35TDB application, or 6116LA35TDB equivalent, key selection criteria include military-grade temperature tolerance, 2V data retention capability, 35ns read cycle timing, standby current ≤40mA (TTL-level) and ≤0.9mA (CMOS-level), and compatibility with legacy 24-pin DIP-based embedded systems.
Technical Context
The 6116LA35TDB implements fully static asynchronous operation-no clocks or refresh required-and uses address decoding logic to drive a 128 × 128 memory array. Its control architecture supports three distinct operational modes: standby (CS high), read (CS & OE low, WE high), and write (CS & WE low).
It integrates TTL-compatible input thresholds (VIH ≥ 2.2V, VIL ≤ 0.8V) and output drive strength (IOH = –4mA, IOL = 8mA), with dual standby power states: ISB = 40mA (TTL-level CS) and ISB1 = 0.9mA (CMOS-level CS). Data retention is guaranteed at VCC = 2.0V across full military temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 16,384 bits (2K × 8), enabling byte-wide data bus interfacing without external demultiplexing |
| Access Time | 35ns max (tAA), defining minimum clock-to-data valid delay in synchronous bus designs |
| Supply Voltage | 5.0V ±10%, compatible with standard TTL/CMOS logic rails and legacy 5V system power domains |
| Data Retention Voltage | 2.0V min (LA version only), allowing operation from backup coin cells during main power loss |
| Standby Current | 0.9mA max (ISB1, CMOS-level CS), reducing system sleep power by >97% vs active mode (ICC1 = 95mA) |
| Operating Temperature | –55°C to +125°C, qualified per MIL-STD-883 Class B for deployment in harsh-environment military platforms |
| Package | 24-pin ceramic DIP (SD24, 300 mil), providing hermetic sealing and thermal stability for high-reliability applications |
Pinout & Package
6116LA35TDB is supplied in a 24-pin ceramic dual in-line package (CDIP), SD24 variant (300 mil width), with gull-wing leads and hermetic ceramic body for military-grade reliability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A10 | Address Inputs | 11-bit address bus supporting 2K-word addressing; all inputs TTL-compatible with VIH ≥ 2.2V |
| I/O0–I/O7 | Bi-directional Data Bus | 8-bit parallel interface; high-impedance state when CS high or OE/WE inactive |
| CS | Chip Select | Active-low enable; drives device into ultra-low-power standby (ISB1 = 0.9mA) when high |
| OE | Output Enable | Active-low control for output drivers; allows read operations without affecting write path |
| WE | Write Enable | Active-low signal initiating write cycle; requires tDW ≥ 20ns data hold before WE high |
| VCC | Power Supply | +5V ±10% supply rail; powers core logic and I/O buffers |
| GND | Ground Reference | 0V return path for all internal circuits and I/O signals |
Key Features
| Feature | Design Value |
|---|---|
| Battery backup data retention | Operates down to 2.0V VCC with ICCDR ≤ 30µA, enabling >10-year data hold from CR2032 cells in cold storage |
| Two-tier standby power management | Supports both TTL-level (ISB = 40mA) and CMOS-level (ISB1 = 0.9mA) chip deselect, optimizing power for different control logic families |
| Fully static asynchronous architecture | Eliminates need for external clocks or refresh circuitry-reducing BOM count and PCB layout complexity in space-constrained systems |
| MIL-STD-883 Class B qualification | Validated for mechanical shock, vibration, temperature cycling, and hermeticity-ensuring reliability in airborne and ground vehicle deployments |
| TTL-compatible I/O interface | Direct connection to legacy 5V microcontrollers and FPGAs without level-shifting components or pull-up resistors |
Applications
| Avionics Flight Control Memory | Tactical Radio Configuration Storage |
|---|---|
Use Scenario: Storing real-time sensor calibration tables and flight envelope limits in digital autopilot units where main power may be interrupted during engine start or transient faults. IC Role / Device Role / Timing Role: Non-volatile configuration memory holding critical flight parameters; retains data during 2V brownout events lasting minutes. Use Value: Eliminates need for external EEPROM or battery-backed SRAM modules-reducing component count and qualification burden while meeting DO-254 safety requirements. | Use Scenario: Holding encrypted channel maps and cryptographic keys in handheld military radios operating across desert and arctic environments. IC Role / Device Role / Timing Role: Secure, temperature-stable memory buffer accessed during boot and rekeying sequences; supports rapid channel switching via 35ns read cycles. Use Value: Enables deterministic <35ns latency for frequency-hopping decisions and meets MIL-STD-810G environmental compliance without derating. |
| Hardened Industrial PLC I/O Mapping | Spacecraft Onboard Telemetry Buffer |
Use Scenario: Caching I/O state mappings and ladder logic operand tables in explosion-proof programmable logic controllers deployed in oil refinery control rooms. IC Role / Device Role / Timing Role: Static RAM serving as fast-access operand store for scan-cycle execution; operates continuously at +85°C ambient with no refresh overhead. Use Value: Delivers deterministic 35ns access within 2ms PLC scan cycles and sustains 100k+ thermal cycles without parameter corruption. | Use Scenario: Buffering housekeeping telemetry packets prior to downlink transmission in low-earth orbit CubeSats exposed to radiation and thermal vacuum. IC Role / Device Role / Timing Role: Radiation-tolerant data staging buffer; leverages CMOS process immunity to alpha-particle soft errors per datasheet claim. Use Value: Provides single-event upset (SEU) resilience without EDAC overhead-critical for resource-constrained nanosatellites with limited processing bandwidth. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar static RAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IS61LV256AL-10TLI | 3.3V supply, 10ns access, SOIC-28 package; no 2V data retention or MIL-STD-883 qualification | Targets commercial industrial controllers-not suitable for military temperature or backup-battery use cases | Select only for new 3.3V designs requiring higher speed and lower voltage; not drop-in compatible |
| HM6116LP-3 | 5V, 35ns, plastic DIP-24; commercial temp range (0°C to +70°C); no battery retention or MIL qualification | Cost-optimized replacement for non-military embedded systems with benign thermal profiles | Acceptable for legacy board repairs where military spec is unnecessary; verify thermal margin at +70°C |
Compared with IS61LV256AL-10TLI and HM6116LP-3, the 6116LA35TDB uniquely delivers military-grade temperature operation, 2V data retention, and MIL-STD-883 Class B validation-making it irreplaceable in avionics, tactical comms, and hardened industrial control where environmental robustness is non-negotiable.
Availability
6116LA35TDB is available at Aetrix Electronics and suitable for avionics flight control, tactical radio configuration storage, and hardened industrial PLC I/O mapping requiring stable component supply across extended lifecycle programs.
Supply support for 6116LA35TDB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and memory solutions for automotive, industrial, and infrastructure markets.
The 6116LA35TDB belongs to Renesas' legacy CMOS static RAM product line, engineered specifically for high-reliability, military-qualified applications demanding zero-refresh operation, wide temperature tolerance, and battery-backed data integrity.
FAQ
What is the maximum operating temperature range for the 6116LA35TDB?
The 6116LA35TDB is rated for –55°C to +125°C operation and is fully compliant with MIL-STD-883 Class B environmental testing. This specification is confirmed in the Absolute Maximum Ratings table and reinforced by military-grade packaging (SD24 ceramic DIP). The 6116LA35TDB maintains full functionality-including 35ns access time and 2V data retention-across this entire range without derating.
Does the 6116LA35TDB support true data retention at 2V, and what is the typical current draw in that mode?
Yes, the 6116LA35TDB supports guaranteed data retention at VCC = 2.0V, as specified in the Data Retention Characteristics table. In this mode, ICCDR is ≤30µA across the full military temperature range. The 6116LA35TDB achieves this via optimized CMOS leakage control and is explicitly designated "LA" (Low-power, Battery Backup) in its part number to distinguish it from the standard-power SA variants.
What package type and pin count does the 6116LA35TDB use?
The 6116LA35TDB uses a 24-pin ceramic dual in-line package (CDIP) with SD24 footprint (300 mil width), as documented in the Ordering Information table and Pin Configurations diagram. This hermetically sealed package provides superior thermal stability and moisture resistance compared to plastic DIP or SOIC variants, aligning with its military qualification requirements.
How does the standby power consumption of the 6116LA35TDB compare between TTL-level and CMOS-level chip select?
The 6116LA35TDB offers two standby modes: ISB = 40mA max when CS is held at TTL-high (>2.2V), and ISB1 = 0.9mA max when CS is driven to CMOS-high (>VCC – 0.2V). This dual-threshold design allows system designers to optimize power savings based on host controller output logic family-maximizing efficiency in mixed-signal or FPGA-based systems.
Is the 6116LA35TDB pin-compatible with other members of the IDT6116SA/LA family?
Yes, the 6116LA35TDB shares identical pinout, signal definitions, and functional behavior with all IDT6116SA/LA variants-including 6116SA20TDB and 6116LA25TDB-as confirmed by the unified Pin Description table and Functional Block Diagram. All variants use the same 24-pin SD24 ceramic DIP package and support identical control protocols (CS/OE/WE timing), enabling direct speed-grade substitution on existing PCBs.
6116LA35TDB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 24-CDIP (0.300", 7.62mm)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Asynchronous
- Memory Size:
- 16Kbit
- Memory Organization:
- 2K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 35ns
- Access Time:
- 35 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 24-CDIP
6116LA35TDB FAQ
1.How can I place an order for 6116LA35TDB through Aetrix?
Please submit a Request for Quotation (RFQ) for 6116LA35TDB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 6116LA35TDB reliable?
The price and inventory of 6116LA35TDB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 6116LA35TDB is usually 5 days.
3.What payment methods are accepted for 6116LA35TDB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 6116LA35TDB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 6116LA35TDB?
6116LA35TDB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 6116LA35TDB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 6116LA35TDB?
For technical support, including 6116LA35TDB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 6116LA35TDB requirements.
6.How does Aetrix verify that 6116LA35TDB is sourced from the original manufacturer or authorized distributors?
All 6116LA35TDB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 6116LA35TDB meets industry standards.
7.What is the process for return or replacement of 6116LA35TDB?
All 6116LA35TDB units undergo pre-shipment inspection (PSI). If there is an issue with 6116LA35TDB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 6116LA35TDB part is unused and in its original packaging.
Return procedure for 6116LA35TDB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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