Renesas 6116LA90TDB
- Part No.:
- 6116LA90TDB
- Manufacturer:
- Renesas
- Category:
- Memory
- Package:
- 24-CDIP (0.300", 7.62mm)
- Datasheet:
-
6116LA90TDB.pdf
- Description:
- IC SRAM 16KBIT PARALLEL 24CDIP
- Quantity:
- Payment:

- Shipping:

Inventory:4,954
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Product details
Overview
6116LA90TDB from Renesas Electronics is a 16K-bit (2K × 8) low-power CMOS static RAM with 90ns access time, TTL-compatible I/O, and military-grade ceramic DIP-24 packaging. It operates across –55°C to +125°C, supports battery backup data retention at 2V, and consumes ≤0.9mA in full standby mode. Used in avionics control modules requiring nonvolatile SRAM with radiation-tolerant reliability.
For engineers reviewing the 6116LA90TDB datasheet, 6116LA90TDB pinout, 6116LA90TDB application, or 6116LA90TDB equivalent, this page delivers verified timing specs (tRC = 90ns), DC/AC electrical characteristics, military temperature compliance, package footprint details, and real-world substitution guidance - all extracted from Renesas' official 6116SA/LA datasheet (Rev. Jul.17.20).
Technical Context
The 6116LA90TDB implements fully static asynchronous operation with no clocks or refresh required. Its architecture features a 128 × 128 memory array, TTL-compatible input thresholds (VIH = 2.2V min, VIL = 0.8V max), and dual standby modes: TTL-level (ISB = 40mA max) and CMOS-level (ISB1 = 0.9mA max).
It uses advanced CMOS process technology to eliminate alpha-particle soft errors and supports battery-backed data retention at VCC = 2.0V with ICCDR ≤ 300μA over full military temperature range. Chip select (CS) controls automatic entry into low-power standby when asserted high.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Organization | 2K × 8-bit (16,384 bits), byte-wide parallel interface |
| Access Time (tAA) | 90ns max at VCC = 5.0V ±10%, TA = –55°C to +125°C - defines minimum read latency for deterministic timing-critical systems |
| Supply Voltage | 4.5V–5.5V - compatible with standard 5V TTL logic rails without level-shifting |
| Data Retention Voltage | 2.0V min - enables direct connection to backup lithium coin cells without regulation |
| Full Standby Current (ISB1) | 0.9mA max at VCC = 5.5V - enables ultra-low-power hold mode during system sleep |
| Operating Temperature | –55°C to +125°C - qualified per MIL-STD-883 Class B for aerospace and defense platforms |
| Package | Ceramic DIP-24 (SD24), 300-mil width - hermetically sealed, leaded, through-hole mountable |
Pinout & Package
6116LA90TDB is housed in a 24-pin ceramic dual in-line package (CDIP) with 300-mil body width (SD24). Pin numbering follows standard DIP convention with Pin 1 in top-left corner (notch-up orientation).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A10 | Address Inputs | 11-bit address bus selecting one of 2K locations; TTL-compatible, no pull-ups required |
| I/O0–I/O7 | Bi-directional Data Bus | 8-bit TTL-compatible data path; high-impedance when CS = HIGH or OE = HIGH |
| CS | Chip Select | Active-low enable; drives device into full standby (ISB1) when HIGH, enabling system-level power gating |
| WE | Write Enable | Active-low write control; latches data on falling edge when CS = LOW |
| OE | Output Enable | Active-low output control; enables read data only when CS = LOW and OE = LOW |
| VCC | Power Supply | +5V supply pin; decoupling capacitor (0.1μF) required within 10mm for noise immunity |
| GND | Ground Reference | Signal and power ground return; must be connected to low-impedance plane |
Key Features
| Feature | Design Value |
|---|---|
| Battery backup data retention | Operates down to 2.0V with ≤300μA retention current - eliminates need for external supervisor ICs in backup circuits |
| CMOS process soft-error immunity | Virtually eliminates alpha-particle-induced bit flips - critical for high-reliability space and avionics applications |
| Two-tier standby power control | ISB = 40mA (TTL-level CS) and ISB1 = 0.9mA (CMOS-level CS) - allows flexible power-state management based on control logic voltage |
| MIL-STD-883 Class B qualification | Fully tested per military screening including thermal cycling, burn-in, and hermeticity - ensures field reliability in harsh environments |
| TTL-compatible I/O | Direct interface with legacy 5V microcontrollers and FPGAs without level translators or bus buffers |
Applications
| Avionics Flight Control Unit | Secure Military Radio Baseband Processor |
|---|---|
Use Scenario: Real-time storage of flight parameter buffers and PID controller coefficients in airborne autopilot hardware. IC Role / Device Role / Timing Role: Nonvolatile scratchpad memory holding mission-critical state variables during power transitions. Use Value: 90ns tAA enables sub-microsecond register reloads; 2V data retention preserves configuration across brownouts without supercapacitor support. | Use Scenario: Storing encrypted key material and channel equalization tables in Type 1 cryptographic radios operating in extended temperature ranges. IC Role / Device Role / Timing Role: Secure, tamper-resistant SRAM buffer isolated from main processor bus during encryption cycles. Use Value: MIL-STD-883 Class B qualification ensures operation at –55°C launch and +125°C desert deployment; CMOS soft-error immunity prevents corruption of crypto keys. |
| Spacecraft Onboard Telemetry Logger | Tactical Vehicle Engine Control Module |
Use Scenario: Buffering sensor telemetry (accelerometer, gyroscope, thermal) between periodic downlink bursts in LEO satellites. IC Role / Device Role / Timing Role: Radiation-hardened local memory staging raw sensor data before compression and transmission. Use Value: Hermetic ceramic DIP-24 package resists outgassing in vacuum; 0.9mA ISB1 minimizes power draw during idle telemetry intervals. | Use Scenario: Holding calibration maps and fault-code history in diesel engine ECUs exposed to under-hood thermal cycling. IC Role / Device Role / Timing Role: High-reliability shadow RAM mirroring flash-resident firmware parameters for fast runtime access. Use Value: –55°C to +125°C operation covers cold-start to peak exhaust heat; 90ns access ensures real-time fuel injection timing accuracy. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar static RAM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| IS61LV25616AL-10TLI | 3.3V-only supply, 10ns access, 256K × 16 organization - higher density but incompatible voltage and pinout | Targets modern low-voltage embedded systems; not suitable for 5V legacy or military designs | Select only if migrating to 3.3V architecture and redesigning PCB layout and power delivery |
| AS6C4008-90PCN | 5V supply, 90ns access, same 2K × 8 organization and DIP-24 package - pin-compatible with identical timing and DC specs | Commercial-grade (0°C to +70°C); lacks MIL-STD-883 qualification and 2V data retention | Valid drop-in replacement for non-military applications where extended temperature and battery backup are not required |
Compared with 6116LA90TDB, IS61LV25616AL-10TLI offers faster speed and larger capacity but requires full system voltage and interface redesign, while AS6C4008-90PCN provides identical functionality in commercial grade - making it a true functional substitute where military qualification is unnecessary.
Availability
6116LA90TDB is available at Aetrix Electronics and suitable for avionics control units, secure radio basebands, spacecraft telemetry loggers, and tactical vehicle ECUs requiring stable component supply across extended temperature and long product lifecycles.
Supply support for 6116LA90TDB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering microcontrollers, analog, power, and memory solutions for automotive, industrial, and infrastructure markets.
The 6116SA/LA family was designed specifically for high-reliability, radiation-tolerant, and extended-temperature applications - targeting aerospace, defense, and industrial control systems where data integrity and operational continuity are non-negotiable.
FAQ
What is the maximum operating temperature range for the 6116LA90TDB?
The 6116LA90TDB is rated for –55°C to +125°C operation and is fully qualified to MIL-STD-883 Class B. This specification is confirmed in the Renesas 6116SA/LA datasheet (Rev. Jul.17.20), Table "Recommended Operating Temperature and Supply Voltage", and applies directly to the 6116LA90TDB variant with SD24 ceramic DIP packaging.
Does the 6116LA90TDB support battery backup data retention, and at what voltage?
Yes, the 6116LA90TDB supports battery backup data retention at VCC = 2.0V minimum, with typical retention current ≤300μA across the full military temperature range. This capability is exclusive to the LA version and is documented in the "Data Retention Characteristics" table (Table 10) of the Renesas 6116SA/LA datasheet.
Is the 6116LA90TDB pin-compatible with the 6116SA90TDB?
Yes, the 6116LA90TDB and 6116SA90TDB share identical pinout, package (SD24 ceramic DIP-24), and AC/DC electrical interface specifications. The only functional difference is power consumption: the LA version adds 2V data retention and lower standby current (ISB1 = 0.9mA vs SA's 10mA), as confirmed in Tables 8 and 10 of the Renesas datasheet.
What is the read cycle time (tRC) specification for the 6116LA90TDB?
The 6116LA90TDB has a guaranteed maximum read cycle time (tRC) of 90ns at VCC = 5.0V ±10% and TA = –55°C to +125°C. This value is explicitly listed in the "AC Electrical Characteristics" table (page 6) for part number 6116LA90TDB under the "90" speed grade column.
Which package type does the 6116LA90TDB use, and is it hermetically sealed?
The 6116LA90TDB uses the SD24 package: a 24-pin ceramic dual in-line package with 300-mil width. As stated in the "Ordering Information" section (page 11) and "Description" (page 1), SD24 denotes a ceramic DIP, which is inherently hermetically sealed - a requirement for MIL-STD-883 Class B qualification and critical for moisture resistance in aerospace deployments.
6116LA90TDB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 24-CDIP (0.300", 7.62mm)
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Volatile
- Memory Format:
- SRAM
- Technology:
- SRAM - Asynchronous
- Memory Size:
- 16Kbit
- Memory Organization:
- 2K x 8
- Memory Interface:
- Parallel
- Clock Frequency:
- -
- Write Cycle Time - Word, Page:
- 90ns
- Access Time:
- 90 ns
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 24-CDIP
6116LA90TDB FAQ
1.How can I place an order for 6116LA90TDB through Aetrix?
Please submit a Request for Quotation (RFQ) for 6116LA90TDB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 6116LA90TDB reliable?
The price and inventory of 6116LA90TDB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 6116LA90TDB is usually 5 days.
3.What payment methods are accepted for 6116LA90TDB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 6116LA90TDB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 6116LA90TDB?
6116LA90TDB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 6116LA90TDB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 6116LA90TDB?
For technical support, including 6116LA90TDB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 6116LA90TDB requirements.
6.How does Aetrix verify that 6116LA90TDB is sourced from the original manufacturer or authorized distributors?
All 6116LA90TDB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 6116LA90TDB meets industry standards.
7.What is the process for return or replacement of 6116LA90TDB?
All 6116LA90TDB units undergo pre-shipment inspection (PSI). If there is an issue with 6116LA90TDB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 6116LA90TDB part is unused and in its original packaging.
Return procedure for 6116LA90TDB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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