Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

Renesas 70T3589S166DR

Name: 70T3589S166DR
Brand: Renesas
SKU: 70T3589S166DR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: 70T3589S166DR

Manufacturer:: Renesas

Category:: Memory

Package:: 208-BFQFP

Datasheet:: 70T3589S166DR.pdf

Description:: IC SRAM 2MBIT PARALLEL 208PQFP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,670

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

70T3589S166DR from Integrated Device Technology is a high-speed 256K × 36-bit synchronous dual-port SRAM with true dual-port architecture enabling simultaneous read/write access to the same memory location. It operates at 166MHz (3.6ns access), supports independent 2.5V core and selectable 2.5V/3.3V I/O supplies per port, and features pipelined or flow-through output modes for burst data transfer in telecom line cards and network packet buffers.

For engineers reviewing the 70T3589S166DR datasheet, 70T3589S166DR pinout, 70T3589S166DR application, or 70T3589S166DR equivalent, key selection criteria include its 208-pin PQFP package, industrial temperature support (−40°C to +85°C), JTAG-compliant boundary scan (not supported in DR208), dual chip enables for depth expansion, and sleep mode (ZZ) for dynamic power management in low-duty-cycle systems.

Technical Context

This device implements fully synchronous operation on both left and right ports with register-controlled inputs-address, data, byte enables, and control signals-all sampled on the rising edge of CLKL/CLKR. Its internal address counter with ADS strobe, CNTEN enable, and REPEAT latch supports burst-mode addressing without external logic.

The memory array uses true dual-port cells with separate input/output paths per port. Power management includes three standby modes (ISB1–ISB4) and a dedicated sleep mode (I_zz ≤ 20mA) activated by ZZL/ZZR, which disables dynamic inputs while preserving JTAG accessibility and static pin functionality.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	256K × 36 bits (9-Mbit total); supports 256K-word depth with 36-bit parallel I/O per port.
Max Clock Frequency	166MHz (t_CYC2 = 6ns min); enables 14.9 Gbps aggregate bandwidth across both ports in pipelined mode.
Access Time	3.6ns (max) at 166MHz pipelined; ensures sub-4ns clock-to-data valid timing for real-time packet buffering.
Supply Voltages	VDD = 2.5V ±100mV (core); VDDQ = 2.5V or 3.3V ±150mV per port (selected via OPTL/OPTR pins).
Operating Temperature	−40°C to +85°C (industrial grade); validated for sustained operation at full speed in base station and industrial control environments.
Package	208-pin plastic quad flat pack (PQFP, DR208); 28mm × 28mm body, 0.5mm lead pitch, RoHS-compliant green variant available.
Power Consumption	I_DD = 450mA max (both ports active, 166MHz); I_zz = 20mA max in sleep mode-critical for thermal budgeting in dense PCB layouts.

Pinout & Package

208-pin PQFP (DR208) package with 28mm × 28mm footprint and 0.5mm lead pitch. All VDD pins require 2.5V; VDDQ pins must match OPT pin configuration (3.3V if OPT = VDD, 2.5V if OPT = VSS). VSS pins connect to ground. JTAG is not supported in this package variant.

Pin/Terminal	Circuit Role	Design Meaning
CLKL / CLKR	Port clock input	Synchronous edge-triggered timing reference for all left/right port operations; no internal PLL required.
A0L–A15L / A0R–A15R	Address inputs	16-bit address bus per port; A16/A17 are No Connect for 70T3589-reduces routing complexity vs. higher-density variants.
I/O0L–I/O35L / I/O0R–I/O35R	Bidirectional data bus	36-bit parallel interface per port; byte enables (BE0–BE3) allow 9-bit granularity writes without masking logic.
CE0L/CE1L / CE0R/CE1R	Dual chip enables	Independent port gating; CE0=low + CE1=high enables memory access-supports seamless depth expansion using multiple devices.
PL/FTL / PL/FTR	Output mode select	Configures pipelined (VIH) or flow-through (VIL) output timing; determines t_CD latency and cycle time requirements.
ZZL / ZZR	Sleep mode control	Asynchronous assertion disables dynamic inputs (except JTAG), reducing current to ≤20mA while retaining state.
INTL / INTR / COLL / COLR	Status flags	Open-drain interrupt/collision outputs signal concurrent access conflicts or completion events to host controller.

Key Features

Feature	Design Value
True dual-port memory cell architecture	Enables simultaneous independent read/write to identical addresses-eliminates arbitration logic in shared-buffer applications.
Configurable I/O voltage per port	OPTL/OPTR pins independently set each port's VDDQ to 2.5V or 3.3V, allowing interfacing with mixed-voltage SoCs or FPGAs.
Dual-cycle deselect (DCD)	Chip enables are double-buffered in pipelined mode, preventing partial writes during rapid CE toggling in burst transfers.
Hardware address counter with repeat	ADSL/ADSR strobes load initial address; CNTENL/CNTENR enable auto-increment; REPEATL/REPEATR latch last valid address for burst restart.
Industrial-grade timing validation	All AC parameters-including t_CD2 = 3.6ns, t_SA = 1.7ns, and t_ZZRC = 3 cycles-guaranteed over −40°C to +85°C at 166MHz.

Applications

Telecom Line Card Buffer	Network Packet Processor Interface
Use Scenario: Storing incoming/outgoing ATM or Ethernet frames in carrier-grade DSLAMs and OLTs where deterministic latency is mandatory. IC Role / Device Role / Timing Role: Dual-port SRAM acts as a non-blocking first-in-first-out (FIFO) buffer between line interface ASIC and traffic manager, with left port accepting ingress data and right port feeding egress scheduler. Use Value: 3.6ns access time and pipelined output mode ensure sub-4ns data availability for 166MHz packet processing clocks, meeting ITU-T G.984.3 jitter budgets.	Use Scenario: Interfacing multi-core packet classification engines with shared lookup tables in enterprise switches. IC Role / Device Role / Timing Role: Provides concurrent read access to TCAM result caches by two CPU cores-one core writes new entries while the other reads match results. Use Value: True dual-port architecture eliminates arbitration delays; 36-bit width matches typical classifier output width, avoiding data splitting across multiple devices.
Industrial PLC Data Exchange	Radar Signal Processing FIFO
Use Scenario: Real-time exchange of sensor data and control commands between motion controller and I/O module in CNC machines. IC Role / Device Role / Timing Role: Serves as a synchronized handshake buffer: left port receives analog-to-digital conversion results from ADC interface; right port delivers interpolated position commands to servo driver. Use Value: Industrial temperature rating (−40°C to +85°C) and guaranteed 166MHz operation ensure reliability in uncooled control cabinets; ZZ sleep mode reduces idle power by >90%.	Use Scenario: Temporary storage of digitized RF samples between ADC and FFT engine in phased-array radar front ends. IC Role / Device Role / Timing Role: Acts as a ping-pong buffer: one port accepts streaming 12-bit IQ samples at 100+ MSPS; the other port feeds processed blocks to DSP core. Use Value: 256K × 36 capacity holds >1M samples; pipelined mode aligns sample delivery with FFT pipeline stages, eliminating inter-stage stalls.

Telecom Line Card Buffer

Network Packet Processor Interface

Use Scenario: Storing incoming/outgoing ATM or Ethernet frames in carrier-grade DSLAMs and OLTs where deterministic latency is mandatory.

IC Role / Device Role / Timing Role: Dual-port SRAM acts as a non-blocking first-in-first-out (FIFO) buffer between line interface ASIC and traffic manager, with left port accepting ingress data and right port feeding egress scheduler.

Use Value: 3.6ns access time and pipelined output mode ensure sub-4ns data availability for 166MHz packet processing clocks, meeting ITU-T G.984.3 jitter budgets.

Use Scenario: Interfacing multi-core packet classification engines with shared lookup tables in enterprise switches.

IC Role / Device Role / Timing Role: Provides concurrent read access to TCAM result caches by two CPU cores-one core writes new entries while the other reads match results.

Use Value: True dual-port architecture eliminates arbitration delays; 36-bit width matches typical classifier output width, avoiding data splitting across multiple devices.

Industrial PLC Data Exchange

Radar Signal Processing FIFO

Use Scenario: Real-time exchange of sensor data and control commands between motion controller and I/O module in CNC machines.

IC Role / Device Role / Timing Role: Serves as a synchronized handshake buffer: left port receives analog-to-digital conversion results from ADC interface; right port delivers interpolated position commands to servo driver.

Use Value: Industrial temperature rating (−40°C to +85°C) and guaranteed 166MHz operation ensure reliability in uncooled control cabinets; ZZ sleep mode reduces idle power by >90%.

Use Scenario: Temporary storage of digitized RF samples between ADC and FFT engine in phased-array radar front ends.

IC Role / Device Role / Timing Role: Acts as a ping-pong buffer: one port accepts streaming 12-bit IQ samples at 100+ MSPS; the other port feeds processed blocks to DSP core.

Use Value: 256K × 36 capacity holds >1M samples; pipelined mode aligns sample delivery with FFT pipeline stages, eliminating inter-stage stalls.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port SRAM applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
CY7C1362BV33-166AXC	3.3V core supply; no 2.5V option; 166MHz max in commercial temp only (0°C to +70°C); 208-pin TQFP package.	Lacks industrial temperature support and dual-voltage I/O flexibility; requires redesign of power delivery network.	Select only for cost-sensitive commercial applications where 2.5V core and extended temperature are not required.
IDT70V27L15PF8	Lower density (128K × 18); 15ns access; 3.3V-only I/O; 100MHz max; 128-pin PQFP.	Insufficient bandwidth and capacity for 166MHz packet buffering; suitable only for legacy control-plane buffers.	Consider only for backward-compatible upgrades where bandwidth and density requirements are relaxed.

Compared with CY7C1362BV33-166AXC and IDT70V27L15PF8, the 70T3589S166DR uniquely combines industrial temperature operation, 2.5V core + flexible I/O voltage, and 166MHz pipelined performance in a single 208-pin PQFP-enabling drop-in replacement in thermally demanding, mixed-voltage systems without layout or power redesign.

Availability

70T3589S166DR is available at Aetrix Electronics and suitable for telecom infrastructure, industrial automation, and radar signal processing requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 70T3589S166DR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Integrated Device Technology (IDT), now part of Renesas Electronics, designs high-performance timing, memory, and interface solutions for communications, computing, and industrial markets.

The 70T35xx family targets high-bandwidth, low-latency data buffering in synchronous systems-specifically engineered for telecom line cards, network processors, and real-time control where deterministic access timing and dual-port concurrency are critical.

FAQ

What is the maximum operating frequency of the 70T3589S166DR in industrial temperature range?

The 70T3589S166DR is rated for 166MHz operation across the full industrial temperature range (−40°C to +85°C), with guaranteed t_CYC2 = 6ns minimum and t_CD2 = 3.6ns maximum in pipelined mode. This specification is validated per datasheet Table 11 and applies exclusively to the DR208 (208-pin PQFP) package variant.

Does the 70T3589S166DR support JTAG boundary scan?

No, the 70T3589S166DR does not support JTAG boundary scan. As explicitly stated in the datasheet Note 9 on page 4, JTAG functionality (TCK, TMS, TDI, TDO, TRST) is not implemented in the DR208 package due to pin count limitations. JTAG is only available in BGA package variants (BC256/BCG256/BF208/BFG208) of the 70T35xx family.

How does the sleep mode (ZZ) function on the 70T3589S166DR?

When ZZL or ZZR is asserted high, the 70T3589S166DR enters sleep mode, disabling all dynamic inputs (except JTAG pins, which remain functional) and reducing current draw to ≤20mA. Static inputs-including PL/FTx, OPTx, and the ZZ pins themselves-retain their states. Recovery requires 3 clock cycles after ZZ deassertion, as specified in t_ZZRC (Table 11).

Can both ports of the 70T3589S166DR operate at different I/O voltages simultaneously?

Yes, the 70T3589S166DR supports independent I/O voltage selection per port: OPTL sets left-port VDDQL to 2.5V (if tied to VSS) or 3.3V (if tied to VDD), and OPTR sets right-port VDDQR identically. This allows one port to interface with a 2.5V FPGA while the other connects to a 3.3V microcontroller-without level-shifting circuitry.

What is the purpose of the REPEAT signal in the 70T3589S166DR address counter?

The REPEATL/REPEATR signal resets the internal address counter to the last valid address loaded via ADSL/ADSR, enabling efficient burst-mode restarts. Unlike auto-increment, REPEAT preserves the final address after a sequence-critical for circular buffer management in packet reassembly or DMA ring buffers without software intervention.

70T3589S166DR Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: -

Package/Case:: 208-BFQFP

Packaging:: Tray

Product Status:: Obsolete

Programmable:: Not Verified

Memory Type:: Volatile

Memory Format:: SRAM

Technology:: SRAM - Dual Port, Synchronous

Memory Size:: 2Mbit

Memory Organization:: 64K x 36

Memory Interface:: Parallel

Clock Frequency:: 166 MHz

Write Cycle Time - Word, Page:: -

Access Time:: 3.6 ns

Voltage - Supply:: 2.4V ~ 2.6V

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 208-PQFP (28x28)

70T3589S166DR FAQ

1.How can I place an order for 70T3589S166DR through Aetrix?

Please submit a Request for Quotation (RFQ) for 70T3589S166DR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 70T3589S166DR reliable?

The price and inventory of 70T3589S166DR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 70T3589S166DR is usually 5 days.

3.What payment methods are accepted for 70T3589S166DR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 70T3589S166DR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 70T3589S166DR?

70T3589S166DR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 70T3589S166DR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 70T3589S166DR?

For technical support, including 70T3589S166DR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 70T3589S166DR requirements.

6.How does Aetrix verify that 70T3589S166DR is sourced from the original manufacturer or authorized distributors?

All 70T3589S166DR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 70T3589S166DR meets industry standards.

7.What is the process for return or replacement of 70T3589S166DR?

All 70T3589S166DR units undergo pre-shipment inspection (PSI). If there is an issue with 70T3589S166DR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 70T3589S166DR part is unused and in its original packaging.

Return procedure for 70T3589S166DR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…