Renesas 70V3589S133DRG

Overview

70V3589S133DRG from IDT (now Renesas) is a high-speed 128K × 36-bit synchronous dual-port SRAM with true dual-port architecture enabling simultaneous read/write access to the same memory location from independent left and right ports. It operates at 133MHz (7.5ns cycle time), supports selectable pipelined or flow-through output modes, features dual chip enables for depth expansion, and delivers 12Gbps aggregate bandwidth. It is used in high-throughput packet buffering and real-time inter-processor communication systems.

For engineers reviewing the 70V3589S133DRG datasheet, 70V3589S133DRG pinout, 70V3589S133DRG application, or 70V3589S133DRG equivalent, key selection criteria include its 133MHz industrial-grade timing (–40°C to +85°C), dual-voltage I/O support (2.5V/3.3V per port), JTAG IEEE 1149.1 compliance, and 208-pin PQFP package compatibility with legacy board layouts.

Technical Context

This device implements fully synchronous operation on both ports with registered address, data, and control inputs-enabling minimal setup (1.7ns) and hold (0.5ns) times at 133MHz. Its dual-port memory array allows concurrent access without arbitration logic, while the integrated address counter with repeat and enable features supports burst-mode sequential addressing.

The device supports independent I/O voltage selection per port via OPTL/OPTR pins, allowing mixed-voltage system interfacing (e.g., 3.3V left port ↔ 2.5V right port). Dual-cycle deselect (DCD) in pipelined mode ensures clean bus release during chip disable transitions, critical for multi-device depth-expanded configurations.

Key Specifications

Pinout & Package

70V3589S133DRG is packaged in a 208-pin Plastic Quad Flatpack (PQFP) with 0.65mm lead pitch and 28mm × 28mm body size. Pin assignments follow standard dual-port SRAM layout with mirrored left/right port signal groups, dedicated OPT and PL/FT control pins, and segregated VDD/VDDQ/VSS rails.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port SRAM applications.

Compared with CY7C1362BV33-133BZXI and AS7C312836PFSI-133, the 70V3589S133DRG uniquely combines per-port I/O voltage selection, IEEE 1149.1 JTAG, and 208-pin PQFP packaging-making it the only drop-in solution for upgrading legacy industrial systems requiring mixed-voltage interoperability and production test coverage.

Availability

70V3589S133DRG is available at Aetrix Electronics and suitable for packet buffering, inter-processor communication, burst-mode video capture, and industrial PLC data exchange requiring stable component supply across extended product lifecycles.

Supply support for 70V3589S133DRG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics (formerly Integrated Device Technology) is a global semiconductor leader specializing in high-performance memory, timing, and connectivity solutions for communications, computing, and industrial markets.

The IDT70V3589 family was designed specifically for high-bandwidth, low-latency dual-port memory applications in networking equipment, real-time signal processing, and mission-critical control systems-emphasizing deterministic timing, mixed-voltage interoperability, and production testability.

FAQ

What is the maximum operating frequency of the 70V3589S133DRG under industrial temperature conditions?

The 70V3589S133DRG is rated for 133MHz operation across the full industrial temperature range of –40°C to +85°C. This is confirmed by AC electrical specifications in Table 11 of the datasheet, where tCYC2 (pipelined clock cycle time) is specified at 7.5ns max, corresponding to 133MHz. The device does not support 166MHz operation in industrial grade-only commercial grade variants do.

Does the 70V3589S133DRG support independent I/O voltage selection on left and right ports?

Yes, the 70V3589S133DRG supports independent I/O voltage selection via OPTL and OPTR pins. Setting OPTL to VIL (0V) configures the left port for 2.5V I/O operation with VDDQL = 2.5V, while setting OPTR to VIH (3.3V) configures the right port for 3.3V I/O with VDDQR = 3.3V. This is explicitly defined in Note 3 on page 5 of the datasheet.

What package type is used for the 70V3589S133DRG, and is it RoHS compliant?

The 70V3589S133DRG uses a 208-pin Plastic Quad Flatpack (PQFP) package, as indicated by the "DRG" suffix and confirmed in the Pin Configuration section (page 4). It is a green (RoHS-compliant) part-this is stated in the Features list on page 1 and further detailed in the Ordering Information section of the full datasheet.

How does the address counter function in the 70V3589S133DRG, and what role does REPEAT play?

The address counter in the 70V3589S133DRG increments automatically on each rising CLK edge when CNTEN is asserted (VIL). REPEAT resets the counter to the last valid address loaded via ADS-enabling looped burst access without host intervention. As clarified in Truth Table III (page 6), REPEAT is independent of CE0/CE1 and remains active even during chip deselect, making it ideal for circular buffer implementations.

Is JTAG boundary-scan supported on the 70V3589S133DRG, and which signals are required?

Yes, the 70V3589S133DRG supports IEEE 1149.1 JTAG boundary-scan via five dedicated pins: TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data In), TDO (Test Data Out), and TRST (Test Reset). These are documented in the Pin Names table (page 5) and functional block diagram (page 1), confirming full TAP controller integration for production test and debug.