Renesas 70V3589S133DRGI

Overview

70V3589S133DRGI from IDT (now Renesas) is a high-speed 128K x 36-bit synchronous dual-port static RAM with true dual-port architecture enabling simultaneous read/write access to the same memory location from independent left and right ports. It operates at 133MHz (7.5ns cycle time), supports selectable pipelined or flow-through output modes, and features dual chip enables for seamless depth expansion in telecom packet buffering applications.

For engineers reviewing the 70V3589S133DRGI datasheet, 70V3589S133DRGI pinout, 70V3589S133DRGI application, or 70V3589S133DRGI equivalent, key selection criteria include its 133MHz industrial-grade timing, independent 2.5V/3.3V I/O voltage support per port, JTAG IEEE 1149.1 compliance, and 208-pin fpBGA package with validated pin mapping for high-density PCB layouts.

Technical Context

This device implements fully synchronous dual-port operation with register-controlled address, data, and control inputs on both ports-enabling minimal setup (1.7ns) and hold (0.5ns) times at 133MHz. Its self-timed write architecture achieves fast 4.2ns clock-to-data-out in pipelined mode while maintaining full port independence.

The memory integrates dual byte-enable groups (BE0–BE3 per port) for 9-bit granularity, counter-enabled sequential addressing with repeat functionality, and Dual Cycle Deselect (DCD) for pipelined output stability. JTAG boundary-scan support enables in-system testability without requiring external test fixtures.

Key Specifications

Pinout & Package

70V3589S133DRGI is packaged in a 208-pin fine-pitch Ball Grid Array (fpBGA) with 0.8mm ball pitch and 15mm × 15mm body size. All VDD pins require 3.3V supply; VDDQL/VDDQR must match selected I/O voltage (2.5V or 3.3V) per port based on OPTL/OPTR logic level.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-port SRAM applications.

Compared with CY7C1362BV33-133BZI and AS7C3256A-133JCIN, the 70V3589S133DRGI uniquely delivers full 128K×36 capacity, per-port 2.5V/3.3V I/O selection, integrated JTAG, and counter-repeat functionality-making it the only option supporting scalable, testable, and flexible-width shared memory in demanding industrial and telecom designs.

Availability

70V3589S133DRGI is available at Aetrix Electronics and suitable for telecom infrastructure, industrial automation, and radar signal processing applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for 70V3589S133DRGI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics (formerly Integrated Device Technology) is a global semiconductor leader specializing in high-performance memory, timing, and analog solutions for communications and industrial markets.

The 70V3589S133DRGI belongs to IDT's high-speed synchronous dual-port SRAM product line, engineered specifically for deterministic, low-latency shared memory in packet-switched networks and real-time embedded systems.

FAQ

What is the maximum operating frequency of the 70V3589S133DRGI in industrial temperature range?

The 70V3589S133DRGI is rated for 133MHz operation (7.5ns cycle time) across the full industrial temperature range of −40°C to +85°C. This is confirmed in the AC Electrical Characteristics table (Table 11) under the "70V3599/89S133 Com'l & Ind" column, where tCYC2 (Pipelined Clock Cycle Time) has a maximum of 7.5ns. The device does not support 166MHz operation in industrial grade.

Does the 70V3589S133DRGI support independent I/O voltage selection on left and right ports?

Yes, the 70V3589S133DRGI supports independent I/O voltage selection: OPTL configures the left port's I/O voltage (2.5V or 3.3V), and OPTR configures the right port's I/O voltage. When OPTL = VIH (3.3V), VDDQL must be 3.3V; when OPTL = VIL (0V), VDDQL must be 2.5V-and similarly for OPTR/VDDQR. This enables mixed-voltage system interfacing without external level shifters.

What is the function of the REPEAT pin on the 70V3589S133DRGI?

The REPEATL and REPEATR pins on the 70V3589S133DRGI reset the internal address counter to the last valid address loaded via ADSL or ADSR. This enables efficient circular buffer implementation-e.g., in packet FIFOs-where the counter automatically wraps after reaching the end of a defined address range. The repeat address is not preset at power-up and must be initialized via an ADS strobe during system startup.

Is JTAG boundary-scan supported on the 70V3589S133DRGI, and which pins are used?

Yes, the 70V3589S133DRGI fully supports IEEE 1149.1 JTAG boundary-scan. The required pins are TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data In), TDO (Test Data Out), and TRST (Test Reset). These signals are dedicated and do not share functions with memory control pins-ensuring robust in-system testability without compromising memory operation.

What package type is used for the 70V3589S133DRGI, and what are its mechanical dimensions?

The 70V3589S133DRGI uses a 208-pin fine-pitch Ball Grid Array (fpBGA) package with 0.8mm ball pitch. Its body measures approximately 15mm × 15mm × 1.4mm. This package is distinct from the 208-pin PQFP and 256-pin BGA variants-confirmed in the Pin Configuration section (page 3) where "BF208(6)" and "BFG208(6)" denote the fpBGA variant used for the "DRGI" suffix part.